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![Theory: An up counter simply counts from 0 to 9. We can use this circuit to make , This circuit can also be used to make a digital clock. Both Synchronous and Asynchronous counters are capable of counting “Up” or counting “Down”, but their is another more “Universal” type of counter that can count in both directions either Up or Down depending on the state of their input control pin and these are known as Bidirectional Counters. Bidirectional counters, also known as a up down counter. PROGRAMME CODES 4bit up counter: module fbuc(clk,reset,q); input clk,reset; output [3:0]q; reg [3:0]q; always@(clk) begin if(reset) q=0; else if(reset==0&&q<15) q=q+1; end endmodule](https://image.slidesharecdn.com/54-150416032043-conversion-gate01/75/To-designing-counters-using-verilog-code-3-2048.jpg)
![reset = 0;clk = 0; #10; reset = 0;clk = 1; #10; reset = 0;clk = 0; #10; reset = 0;clk = 1; #10; reset = 0;clk = 0; #10; reset = 0;clk = 1; #10; reset = 0;clk = 0; #10; reset = 0;clk = 1; #10; reset = 0;clk = 0; #10; reset = 0;clk = 1; #10; reset = 0;clk = 0; #10; reset = 0;clk = 1; #10; // Add stimulus here end endmodule 4bit down counter module fbdc(clk,reset,q); input clk,reset; output [3:0]q; reg [3:0]q; always@(clk) begin if(reset) q=15; else if(reset==0&&q>0) q=q-1; end](https://image.slidesharecdn.com/54-150416032043-conversion-gate01/75/To-designing-counters-using-verilog-code-6-2048.jpg)
![4b Up down counter module fbudc(clk,reset,up,dn,q); input clk,up,dn,reset; output [3:0]q; reg [3:0]q; always@(clk) begin if (reset) q=0; else if(up) q=q+1; else if(dn) q=q-1; end endmodule](https://image.slidesharecdn.com/54-150416032043-conversion-gate01/75/To-designing-counters-using-verilog-code-10-2048.jpg)
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To designing counters using verilog code
The document describes implementing up, down, and up/down counters using Verilog code. It includes: 1) Code for a 4-bit up counter that counts from 0 to 15 when the clock signal changes. 2) Code for a 4-bit down counter that counts from 15 to 0 when the clock signal changes. 3) Code for a 4-bit up/down counter that counts up when the up signal is high and down when the down signal is high, controlled by the clock.
To designing counters using verilog code
- 1. Experiment No:9 Aim: ToImplement counters. NAME: Shyamveer Singh SECTION: E1207 REG N0: 11205816 ROLL NO: B-54
- 2. Truth Table: Up downcounter: Up counter:
- 3. Theory: An up countersimply counts from 0 to 9. We can use this circuit to make , This circuit can also be used to make a digital clock. Both Synchronous and Asynchronous counters are capable of counting “Up” or counting “Down”, but their is another more “Universal” type of counter that can count in both directions either Up or Down depending on the state of their input control pin and these are known as Bidirectional Counters. Bidirectional counters, also known as a up down counter. PROGRAMME CODES 4bit up counter: module fbuc(clk,reset,q); input clk,reset; output [3:0]q; reg [3:0]q; always@(clk) begin if(reset) q=0; else if(reset==0&&q<15) q=q+1; end endmodule
- 4. reset = 1;clk= 0; // Wait 100 ns for global reset to finish #10; reset = 0;clk = 1; #10; reset = 0;clk = 0; #10; reset = 0;clk = 1; #10; reset = 0;clk = 0; #10; reset = 0;clk = 1; #10; reset = 0;clk = 0; #10; reset = 0;clk = 1; #10; reset = 0;clk = 0; #10; reset = 0;clk = 1; #10; reset = 0;clk = 0; #10; reset = 0;clk = 1;
- 5. #10; reset = 0;clk= 0; #10; reset = 0;clk = 1; #10; reset = 0;clk = 0; #10; reset = 0;clk = 1; #10; // Add stimulus here end endmodule // Initialize Inputs reset = 1;clk = 0; // Wait 100 ns for global reset to finish #10; reset = 0;clk = 1; #10; reset = 0;clk = 0; #10; reset = 0;clk = 1; #10;
- 6. reset = 0;clk= 0; #10; reset = 0;clk = 1; #10; reset = 0;clk = 0; #10; reset = 0;clk = 1; #10; reset = 0;clk = 0; #10; reset = 0;clk = 1; #10; reset = 0;clk = 0; #10; reset = 0;clk = 1; #10; reset = 0;clk = 0; #10; reset = 0;clk = 1; #10; reset = 0;clk = 0; #10; reset = 0;clk = 1; #10; // Add stimulus here end endmodule 4bit down counter module fbdc(clk,reset,q); input clk,reset; output [3:0]q; reg [3:0]q; always@(clk) begin if(reset) q=15; else if(reset==0&&q>0) q=q-1; end
- 7.
- 8. reset = 1;clk= 0; // Wait 100 ns for global reset to finish #10; reset = 0;clk = 1; #10; reset = 0;clk = 0; #10; reset = 0;clk = 1; #10; reset = 0;clk = 0; #10; reset = 0;clk = 1; #10; reset = 0;clk = 0; #10; reset = 0;clk = 1; #10; reset = 0;clk = 0; #10; reset = 0;clk = 1; #10; reset = 0;clk = 0;
- 9. #10; reset = 0;clk= 1; #10; reset = 0;clk = 0; #10; reset = 0;clk = 1; #10; reset = 0;clk = 0; #10; reset = 0;clk = 1; #10; reset = 0;clk = 0; #10; reset = 0;clk = 1; #10; // Add stimulus here end endmodule
- 10. 4b Up downcounter module fbudc(clk,reset,up,dn,q); input clk,up,dn,reset; output [3:0]q; reg [3:0]q; always@(clk) begin if (reset) q=0; else if(up) q=q+1; else if(dn) q=q-1; end endmodule
- 11. clk = 0; reset= 1; up = 1; dn = 0; // Wait 100 ns for global reset to finish #10; clk = 1; reset = 0; up = 1; dn = 0; #10; clk = 0; reset = 0; up = 1; dn = 0; #10; clk = 1; reset = 0; up = 1; dn = 0; #10; clk = 0;
- 12. reset = 0; up= 1; dn = 0; #10; clk = 1; reset = 0; up = 1; dn = 0; #10; clk = 0; reset = 0; up = 1; dn = 0; #10; clk = 1; reset = 0; up = 1; dn = 0; #10; clk = 0; reset = 0; up = 1; dn = 0; #10; clk = 1; reset = 0; up = 1; dn = 0; #10; clk = 0; reset = 0; up = 1; dn = 0; #10; clk = 1; reset = 0; up = 1; dn = 0; #10; clk = 0; reset = 0; up = 1; dn = 0; #10; clk = 1; reset = 0; up = 1; dn = 0; #10;
- 13. clk = 0; reset= 0; up = 1; dn = 0; #10; clk = 1; reset = 0; up = 1; dn = 0; #10; clk = 1; reset = 0; up = 0; dn = 1; #10; clk = 0; reset = 0; up = 0; dn = 1; #10; clk = 1; reset = 0; up = 0; dn = 1; #10; clk = 0; reset = 0; up = 0; dn = 1; #10; clk = 1; reset = 0; up = 0; dn = 1; #10; clk = 0; reset = 0; up = 0; dn = 1; #10; clk = 1; reset = 0; up = 0; dn = 1; #10; clk = 0; reset = 0; up = 0; dn = 1;
- 14. #10; clk = 1; reset= 0; up = 0; dn = 1; #10; clk = 0; reset = 0; up = 0; dn = 1; #10; clk = 1; reset = 0; up = 0; dn = 1; #10; clk = 0; reset = 0; up = 0; dn = 1; #10; clk = 1; reset = 0; up = 0; dn = 1; #10; clk = 0; reset = 0; up = 0; dn = 1; #10; clk = 1; reset = 0; up = 0; dn = 1; #10; clk = 0; reset = 0; up = 0; dn = 1; #10; // Add stimulus here end endmodule