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![Tasks are declared with the keywords task and endtask. Tasks must be used if any one of the following conditions is true for the procedure: • There are delay, timing, or event control constructs in the procedure. • The procedure has zero or more than one output arguments. • The procedure has no input arguments. Input and Output Arguments in Tasks module operation; ... ... parameter delay = 10; reg [15:0] A, B; reg [15:0] AB_AND, AB_OR, AB_XOR; always @(A or B) //whenever A or B changes in value begin //invoke the task bitwise_oper. provide 2 input arguments A, B //Expect 3 output arguments AB_AND, AB_OR, AB_XOR //The arguments must be specified in the same order as they //appear in the task declaration. bitwise_oper(AB_AND, AB_OR, AB_XOR, A, B); end ... ... //define task bitwise_oper task bitwise_oper; output [15:0] ab_and, ab_or, ab_xor; //outputs from the task input [15:0] a, b; //inputs to the task begin #delay ab_and = a & b; ab_or = a | b; ab_xor = a ^ b; end endtask ... endmodule 4Prepared by Anand HD, Dr. AIT, Bengaluru](https://image.slidesharecdn.com/tasksfunctions-200325185418/75/Verilog-Tasks-Functions-4-2048.jpg)
![In this task, the input values passed to the task are A and B. Hence, when the task is entered, a = A and b = B. The three output values are computed after a delay. This delay is specified by the parameter delay, which is 10 units for this example. When the task is completed, the output values are passed back to the calling output arguments. Therefore, AB_AND = ab_and, AB_OR = ab_or, and AB_XOR = ab_xor when the task is completed. Another method of declaring arguments for tasks is the ANSI C style. Task Definition using ANSI C Style Argument Declaration //define task bitwise_oper task bitwise_oper (output [15:0] ab_and, ab_or, ab_xor, input [15:0] a, b); begin #delay ab_and = a & b; ab_or = a | b; ab_xor = a ^ b; end endtask 5Prepared by Anand HD, Dr. AIT, Bengaluru](https://image.slidesharecdn.com/tasksfunctions-200325185418/75/Verilog-Tasks-Functions-5-2048.jpg)
![Example of Re-entrant (Automatic) Tasks: // There are two clocks. // clk2 runs at twice the frequency of clk and is synchronous with clk. module top; reg [15:0] cd_xor, ef_xor; //variables in module top reg [15:0] c, d, e, f; //variables in module top task automatic bitwise_xor; output [15:0] ab_xor; //output from the task input [15:0] a, b; //inputs to the task begin #delay ab_and = a & b; ab_or = a | b; ab_xor = a ^ b; end endtask ... // These two always blocks will call the bitwise_xor task // concurrently at each positive edge of clk. However, since // the task is re-entrant, these concurrent calls will work correctly. always @(posedge clk) bitwise_xor(ef_xor, e, f); - always @(posedge clk2) // twice the frequency as the previous block bitwise_xor(cd_xor, c, d); - endmodule 8Prepared by Anand HD, Dr. AIT, Bengaluru](https://image.slidesharecdn.com/tasksfunctions-200325185418/75/Verilog-Tasks-Functions-8-2048.jpg)
![EXAMPLES Example 1: module simple_task(); task convert; input [7:0] temp_in; output [7:0] temp_out; begin temp_out = (9/5) *( temp_in + 32) end endtask endmodule Example 2; module task_global(); reg [7:0] temp_out; reg [7:0] temp_in; task convert; begin temp_out = (9/5) *( temp_in + 32); end endtask endmodule 9Prepared by Anand HD, Dr. AIT, Bengaluru](https://image.slidesharecdn.com/tasksfunctions-200325185418/75/Verilog-Tasks-Functions-9-2048.jpg)
![Example 3: Calling a Task module task_calling (temp_a, temp_b, temp_c, temp_d); input [7:0] temp_a, temp_c; output [7:0] temp_b, temp_d; reg [7:0] temp_b, temp_d; include "mytask.v" always @ (temp_a) begin convert (temp_a, temp_b); end always @ (temp_c) begin convert (temp_c, temp_d); end endmodule 10Prepared by Anand HD, Dr. AIT, Bengaluru](https://image.slidesharecdn.com/tasksfunctions-200325185418/75/Verilog-Tasks-Functions-10-2048.jpg)
![Example 4: module bus_wr_rd_task(); reg clk,rd,wr,ce; reg [7:0] addr,data_wr,data_rd; reg [7:0] read_data; initial begin clk = 0; read_data = 0; rd = 0; wr = 0; ce = 0; addr = 0; data_wr = 0; data_rd = 0; // Call the write and read tasks here #1 cpu_write(8'h11,8'hAA); #1 cpu_read(8'h11,read_data); #1 cpu_write(8'h12,8'hAB); #1 cpu_read(8'h12,read_data); #1 cpu_write(8'h13,8'h0A); #1 cpu_read(8'h13,read_data); #100 $finish; end // Clock Generator always #1 clk = ~clk; // CPU Read Task task cpu_read; input [7:0] address; output [7:0] data; begin $display ("%g CPU Read task with address : %h", $time, address); $display ("%g -> Driving CE, RD and ADDRESS on to bus", $time); @ (posedge clk); addr = address; ce = 1; rd = 1; @ (negedge clk); data = data_rd; @ (posedge clk); addr = 0; ce = 0; rd = 0; $display ("%g CPU Read data : %h", $time, data); $display ("======================"); end endtask 11Prepared by Anand HD, Dr. AIT, Bengaluru](https://image.slidesharecdn.com/tasksfunctions-200325185418/75/Verilog-Tasks-Functions-11-2048.jpg)
![// CU Write Task task cpu_write; input [7:0] address; input [7:0] data; begin $display ("%g CPU Write task with address : %h Data : %h", $time, address,data); $display ("%g -> Driving CE, WR, WR data and ADDRESS on to bus", $time); @ (posedge clk); addr = address; ce = 1; wr = 1; data_wr = data; @ (posedge clk); addr = 0; ce = 0; wr = 0; $display ("======================"); end endtask 12Prepared by Anand HD, Dr. AIT, Bengaluru](https://image.slidesharecdn.com/tasksfunctions-200325185418/75/Verilog-Tasks-Functions-12-2048.jpg)
![Example: Parity Calculation //Define a module that contains the function calc_parity module parity; ... reg [31:0] addr; reg parity; //Compute new parity whenever address value changes always @(addr) begin parity = calc_parity(addr); //First invocation of calc_parity $display("Parity calculated = %b", calc_parity(addr) ); end ... //define the parity calculation function function calc_parity; input [31:0] address; begin //set the output value appropriately. Use the implicit nternal register calc_parity. calc_parity = ^address; //Return the xor of all address bits. end endfunction ... ... endmodule 15Prepared by Anand HD, Dr. AIT, Bengaluru](https://image.slidesharecdn.com/tasksfunctions-200325185418/75/Verilog-Tasks-Functions-15-2048.jpg)
![Function Definition using ANSI C Style Argument Declaration //define the parity calculation function using ANSI C Style arguments function calc_parity (input [31:0] address); begin //set the output value appropriately. Use the implicit nternal register calc_parity. calc_parity = ^address; //Return the xor of all address bits. end endfunction Example: Left/Right Shifter //Define a module that contains the function shift module shifter; ... //Left/right shifter `define LEFT_SHIFT 1'b0 `define RIGHT_SHIFT 1'b1 reg [31:0] addr, left_addr, right_addr; reg control; //Compute the right- and left-shifted values whenever a new address value appears always @(addr) begin 16Prepared by Anand HD, Dr. AIT, Bengaluru](https://image.slidesharecdn.com/tasksfunctions-200325185418/75/Verilog-Tasks-Functions-16-2048.jpg)
![//call the function defined below to do left and right shift. left_addr = shift(addr, `LEFT_SHIFT); right_addr = shift(addr, `RIGHT_SHIFT); end ... ... //define shift function. The output is a 32-bit value. function [31:0] shift; input [31:0] address; input control; begin //set the output value appropriately based on a control signal. shift = (control == `LEFT_SHIFT) ?(address << 1) : (address >> 1); end endfunction ... ... endmodule 17Prepared by Anand HD, Dr. AIT, Bengaluru](https://image.slidesharecdn.com/tasksfunctions-200325185418/75/Verilog-Tasks-Functions-17-2048.jpg)
![Example: Recursive (Automatic) Functions //Define a factorial with a recursive function module top; ... // Define the function function automatic integer factorial; input [31:0] oper; integer i; begin if (operand >= 2) factorial = factorial (oper -1) * oper; //recursive call else factorial = 1 ; end endfunction // Call the function integer result; initial begin result = factorial(4); // Call the factorial of 4 $display("Factorial of 4 is %0d", result); //Displays 24 end ... endmodule 18Prepared by Anand HD, Dr. AIT, Bengaluru](https://image.slidesharecdn.com/tasksfunctions-200325185418/75/Verilog-Tasks-Functions-18-2048.jpg)
![Constant Functions: A constant function is a regular Verilog HDL function, but with certain restrictions. These functions can be used to reference complex values and can be used instead of constants. Example: Constant Functions //Define a RAM model module ram (...); parameter RAM_DEPTH = 256; input [clogb2(RAM_DEPTH)-1:0] addr_bus; //width of bus computed //by calling constant function defined below, Result of clogb2 = 8, input [7:0] addr_bus; -- //Constant function function integer clogb2(input integer depth); begin for(clogb2=0; depth >0; clogb2=clogb2+1) depth = depth >> 1; end endfunction -- endmodule 20Prepared by Anand HD, Dr. AIT, Bengaluru](https://image.slidesharecdn.com/tasksfunctions-200325185418/75/Verilog-Tasks-Functions-20-2048.jpg)
![Signed Functions: Signed functions allow signed operations to be performed on the function return values Example: Signed Functions module top; -- //Signed function declaration //Returns a 64 bit signed value function signed [63:0] compute_signed(input [63:0] vector); -- -- endfunction -- //Call to the signed function from the higher module if(compute_signed(vector) < -3) begin -- end -- endmodule 21Prepared by Anand HD, Dr. AIT, Bengaluru](https://image.slidesharecdn.com/tasksfunctions-200325185418/75/Verilog-Tasks-Functions-21-2048.jpg)
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Verilog Tasks & Functions
Tasks and functions allow designers to abstract commonly used Verilog code into reusable routines. Tasks can contain timing constructs and pass multiple values through input, output, and inout arguments. Functions must not contain timing constructs and return a single value. Tasks are similar to subroutines while functions are similar to functions in other languages like FORTRAN. Automatic tasks make tasks re-entrant to avoid issues with concurrent calls operating on shared variables.
In this document
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Introduction of the presenter, Anand H D, covering the importance of tasks and functions.
Tasks & functions abstract common functionalities in Verilog code, similar to subroutines/functions in FORTRAN.
Differences between tasks and functions detailed in a tabular format covering execution time, arguments, and return values.
Syntax and examples for declaring tasks in Verilog, emphasizing usage conditions and input/output arguments.
Illustrates the input/output argument concept in tasks with an example of bitwise operations over delays.
Demonstrates task usage with reg variables, showing an initialization and sequence generation tasks.
Discusses 'automatic' tasks that prevent incorrect results when called concurrently by ensuring each call has independent variable space.
Example of re-entrant tasks demonstrating concurrent calls for different clock frequencies without interference.
Presents examples of task usage in module instances illustrating basic task creation and calls in Verilog.
Demonstrates task calling with multiple outputs based on input conditions in inter-module communications.
CPU read/write task implementation showcasing how data operations are synchronized with clock signals.
Continues from the previous slide, detailing implementation of the CPU write operation with necessary log displays.
Demonstrates how the simulator outputs interact with the functions for reading and writing data through tasks.
Introduction to functions in Verilog, conditions for their use, and syntax for function declaration.
Shows how to compute parity in an address value using a function and demonstrates its invocation.
Illustrates function definitions in Verilog with ANSI C style argument declarations, focusing on shifting operations.
Details an example of defining a left/right shift function and its utilization for address handling.
Covers an example of recursive function usage for calculating factorial values in a Verilog module.
Demonstrates calling functions in module context and shows how to handle output from functions.
Defines constant functions and their utility for specific parameter calculations such as RAM depth.
Demonstrates signed functions for performing operations on signed values in software design.
Provides references for further reading and understanding of Verilog HDL principles.
Conclusion of the presentation; slide without specific content.
Verilog Tasks & Functions
- 1. TASKS & FUNCTIONS ByAnand H D Assistant Professor, Dr. AIT, Bengaluru-56 1
- 2. A designer isfrequently required to implement the same functionality at many places in a behavioral design. This means that the commonly used parts should be abstracted into routines and the routines must be invoked instead of repeating the code. Most programming languages provide procedures or subroutines to accomplish this. Verilog provides tasks and functions to break up large behavioral designs into smaller pieces. Tasks and functions allow the designer to abstract Verilog code that is used at many places in the design. Tasks have input, output, and inout arguments; functions have input arguments. Thus, values can be passed into and out from tasks and functions. Considering the analogy of FORTRAN, tasks are similar to SUBROUTINE and functions are similar to FUNCTION. 2Prepared by Anand HD, Dr. AIT, Bengaluru
- 3. Differences between Tasksand Functions: FUNCTIONS TASKS A function can enable another function but not another task. A task can enable other tasks and functions. Functions always execute in 0 simulation time Tasks may execute in non-zero simulation time. Functions must not contain any delay, event, or timing control statements. Tasks may contain delay, event, or timing control statements. Functions must have at least one input argument. They can have more than one input. Tasks may have zero or more arguments of type input, output, or inout. Functions always return a single value. They cannot have output or inout arguments Tasks do not return with a value, but can pass multiple values through output and inout arguments 3 Prepared by Anand HD, Dr. AIT, Bengaluru
- 4. Tasks are declaredwith the keywords task and endtask. Tasks must be used if any one of the following conditions is true for the procedure: • There are delay, timing, or event control constructs in the procedure. • The procedure has zero or more than one output arguments. • The procedure has no input arguments. Input and Output Arguments in Tasks module operation; ... ... parameter delay = 10; reg [15:0] A, B; reg [15:0] AB_AND, AB_OR, AB_XOR; always @(A or B) //whenever A or B changes in value begin //invoke the task bitwise_oper. provide 2 input arguments A, B //Expect 3 output arguments AB_AND, AB_OR, AB_XOR //The arguments must be specified in the same order as they //appear in the task declaration. bitwise_oper(AB_AND, AB_OR, AB_XOR, A, B); end ... ... //define task bitwise_oper task bitwise_oper; output [15:0] ab_and, ab_or, ab_xor; //outputs from the task input [15:0] a, b; //inputs to the task begin #delay ab_and = a & b; ab_or = a | b; ab_xor = a ^ b; end endtask ... endmodule 4Prepared by Anand HD, Dr. AIT, Bengaluru
- 5. In this task,the input values passed to the task are A and B. Hence, when the task is entered, a = A and b = B. The three output values are computed after a delay. This delay is specified by the parameter delay, which is 10 units for this example. When the task is completed, the output values are passed back to the calling output arguments. Therefore, AB_AND = ab_and, AB_OR = ab_or, and AB_XOR = ab_xor when the task is completed. Another method of declaring arguments for tasks is the ANSI C style. Task Definition using ANSI C Style Argument Declaration //define task bitwise_oper task bitwise_oper (output [15:0] ab_and, ab_or, ab_xor, input [15:0] a, b); begin #delay ab_and = a & b; ab_or = a | b; ab_xor = a ^ b; end endtask 5Prepared by Anand HD, Dr. AIT, Bengaluru
- 6. Example : DirectOperation on reg Variables module sequence; ... reg clock; ... initial init_sequence; //Invoke the task init_sequence ... always begin asymmetric_sequence; //Invoke the task asymmetric_sequence end ... ... //Initialization sequence task init_sequence; begin clock = 1'b0; end endtask //define task to generate asymmetric sequence //operate directly on the clock defined in the module. task asymmetric_sequence; begin #12 clock = 1'b0; #5 clock = 1'b1; #3 clock = 1'b0; #10 clock = 1'b1; end endtask ... ... endmodule 6Prepared by Anand HD, Dr. AIT, Bengaluru
- 7. Automatic (Re-entrant) Tasks: Tasksare normally static in nature. All declared items are statically allocated and they are shared across all uses of the task executing concurrently. Therefore, if a task is called concurrently from two places in the code, these task calls will operate on the same task variables. It is highly likely that the results of such an operation will be incorrect. To avoid this problem, a keyword automatic is added in front of the task keyword to make the tasks re-entrant. Such tasks are called automatic tasks. All items declared inside automatic tasks are allocated dynamically for each invocation. Each task call operates in an independent space. Thus, the task calls operate on independent copies of the task variables. This results in correct operation. It is recommended that automatic tasks be used if there is a chance that a task might be called concurrently from two locations in the code. 7Prepared by Anand HD, Dr. AIT, Bengaluru
- 8. Example of Re-entrant(Automatic) Tasks: // There are two clocks. // clk2 runs at twice the frequency of clk and is synchronous with clk. module top; reg [15:0] cd_xor, ef_xor; //variables in module top reg [15:0] c, d, e, f; //variables in module top task automatic bitwise_xor; output [15:0] ab_xor; //output from the task input [15:0] a, b; //inputs to the task begin #delay ab_and = a & b; ab_or = a | b; ab_xor = a ^ b; end endtask ... // These two always blocks will call the bitwise_xor task // concurrently at each positive edge of clk. However, since // the task is re-entrant, these concurrent calls will work correctly. always @(posedge clk) bitwise_xor(ef_xor, e, f); - always @(posedge clk2) // twice the frequency as the previous block bitwise_xor(cd_xor, c, d); - endmodule 8Prepared by Anand HD, Dr. AIT, Bengaluru
- 9. EXAMPLES Example 1: module simple_task(); taskconvert; input [7:0] temp_in; output [7:0] temp_out; begin temp_out = (9/5) *( temp_in + 32) end endtask endmodule Example 2; module task_global(); reg [7:0] temp_out; reg [7:0] temp_in; task convert; begin temp_out = (9/5) *( temp_in + 32); end endtask endmodule 9Prepared by Anand HD, Dr. AIT, Bengaluru
- 10. Example 3: Callinga Task module task_calling (temp_a, temp_b, temp_c, temp_d); input [7:0] temp_a, temp_c; output [7:0] temp_b, temp_d; reg [7:0] temp_b, temp_d; include "mytask.v" always @ (temp_a) begin convert (temp_a, temp_b); end always @ (temp_c) begin convert (temp_c, temp_d); end endmodule 10Prepared by Anand HD, Dr. AIT, Bengaluru
- 11. Example 4: module bus_wr_rd_task(); regclk,rd,wr,ce; reg [7:0] addr,data_wr,data_rd; reg [7:0] read_data; initial begin clk = 0; read_data = 0; rd = 0; wr = 0; ce = 0; addr = 0; data_wr = 0; data_rd = 0; // Call the write and read tasks here #1 cpu_write(8'h11,8'hAA); #1 cpu_read(8'h11,read_data); #1 cpu_write(8'h12,8'hAB); #1 cpu_read(8'h12,read_data); #1 cpu_write(8'h13,8'h0A); #1 cpu_read(8'h13,read_data); #100 $finish; end // Clock Generator always #1 clk = ~clk; // CPU Read Task task cpu_read; input [7:0] address; output [7:0] data; begin $display ("%g CPU Read task with address : %h", $time, address); $display ("%g -> Driving CE, RD and ADDRESS on to bus", $time); @ (posedge clk); addr = address; ce = 1; rd = 1; @ (negedge clk); data = data_rd; @ (posedge clk); addr = 0; ce = 0; rd = 0; $display ("%g CPU Read data : %h", $time, data); $display ("======================"); end endtask 11Prepared by Anand HD, Dr. AIT, Bengaluru
- 12. // CU WriteTask task cpu_write; input [7:0] address; input [7:0] data; begin $display ("%g CPU Write task with address : %h Data : %h", $time, address,data); $display ("%g -> Driving CE, WR, WR data and ADDRESS on to bus", $time); @ (posedge clk); addr = address; ce = 1; wr = 1; data_wr = data; @ (posedge clk); addr = 0; ce = 0; wr = 0; $display ("======================"); end endtask 12Prepared by Anand HD, Dr. AIT, Bengaluru
- 13. Simulator Output: 1 CPUWrite task with address : 11 Data : aa 1 -> Driving CE, WR, WR data and ADDRESS on to bus ====================== 4 CPU Read task with address : 11 4 -> Driving CE, RD and ADDRESS on to bus 7 CPU Read data : aa ====================== 8 CPU Write task with address : 12 Data : ab 8 -> Driving CE, WR, WR data and ADDRESS on to bus ====================== 12 CPU Read task with address : 12 12 -> Driving CE, RD and ADDRESS on to bus 15 CPU Read data : ab ====================== 16 CPU Write task with address : 13 Data : 0a 16 -> Driving CE, WR, WR data and ADDRESS on to bus ====================== 20 CPU Read task with address : 13 20 -> Driving CE, RD and ADDRESS on to bus 23 CPU Read data : 0a ====================== 13Prepared by Anand HD, Dr. AIT, Bengaluru
- 14. Functions: Functions are declaredwith the keywords function and endfunction. Functions are used if all of the following conditions are true for the procedure: •There are no delay, timing, or event control constructs in the procedure. • The procedure returns a single value. • There is at least one input argument. • There are no output or inout arguments. • There are no nonblocking assignments. 14Prepared by Anand HD, Dr. AIT, Bengaluru
- 15. Example: Parity Calculation //Definea module that contains the function calc_parity module parity; ... reg [31:0] addr; reg parity; //Compute new parity whenever address value changes always @(addr) begin parity = calc_parity(addr); //First invocation of calc_parity $display("Parity calculated = %b", calc_parity(addr) ); end ... //define the parity calculation function function calc_parity; input [31:0] address; begin //set the output value appropriately. Use the implicit nternal register calc_parity. calc_parity = ^address; //Return the xor of all address bits. end endfunction ... ... endmodule 15Prepared by Anand HD, Dr. AIT, Bengaluru
- 16. Function Definition usingANSI C Style Argument Declaration //define the parity calculation function using ANSI C Style arguments function calc_parity (input [31:0] address); begin //set the output value appropriately. Use the implicit nternal register calc_parity. calc_parity = ^address; //Return the xor of all address bits. end endfunction Example: Left/Right Shifter //Define a module that contains the function shift module shifter; ... //Left/right shifter `define LEFT_SHIFT 1'b0 `define RIGHT_SHIFT 1'b1 reg [31:0] addr, left_addr, right_addr; reg control; //Compute the right- and left-shifted values whenever a new address value appears always @(addr) begin 16Prepared by Anand HD, Dr. AIT, Bengaluru
- 17. //call the functiondefined below to do left and right shift. left_addr = shift(addr, `LEFT_SHIFT); right_addr = shift(addr, `RIGHT_SHIFT); end ... ... //define shift function. The output is a 32-bit value. function [31:0] shift; input [31:0] address; input control; begin //set the output value appropriately based on a control signal. shift = (control == `LEFT_SHIFT) ?(address << 1) : (address >> 1); end endfunction ... ... endmodule 17Prepared by Anand HD, Dr. AIT, Bengaluru
- 18. Example: Recursive (Automatic)Functions //Define a factorial with a recursive function module top; ... // Define the function function automatic integer factorial; input [31:0] oper; integer i; begin if (operand >= 2) factorial = factorial (oper -1) * oper; //recursive call else factorial = 1 ; end endfunction // Call the function integer result; initial begin result = factorial(4); // Call the factorial of 4 $display("Factorial of 4 is %0d", result); //Displays 24 end ... endmodule 18Prepared by Anand HD, Dr. AIT, Bengaluru
- 19. Example 1: module simple_function(); functionmyfunction; input a, b, c, d; begin myfunction = ((a+b) + (c-d)); end endfunction endmodule Function Call: module function_calling(a, b, c, d, e, f); input a, b, c, d, e ; output f; wire f; `include "myfunction.v" assign f = (myfunction (a,b,c,d)) ? e :0; endmodule 19Prepared by Anand HD, Dr. AIT, Bengaluru
- 20. Constant Functions: A constantfunction is a regular Verilog HDL function, but with certain restrictions. These functions can be used to reference complex values and can be used instead of constants. Example: Constant Functions //Define a RAM model module ram (...); parameter RAM_DEPTH = 256; input [clogb2(RAM_DEPTH)-1:0] addr_bus; //width of bus computed //by calling constant function defined below, Result of clogb2 = 8, input [7:0] addr_bus; -- //Constant function function integer clogb2(input integer depth); begin for(clogb2=0; depth >0; clogb2=clogb2+1) depth = depth >> 1; end endfunction -- endmodule 20Prepared by Anand HD, Dr. AIT, Bengaluru
- 21. Signed Functions: Signed functionsallow signed operations to be performed on the function return values Example: Signed Functions module top; -- //Signed function declaration //Returns a 64 bit signed value function signed [63:0] compute_signed(input [63:0] vector); -- -- endfunction -- //Call to the signed function from the higher module if(compute_signed(vector) < -3) begin -- end -- endmodule 21Prepared by Anand HD, Dr. AIT, Bengaluru
- 22. References • Samir Palnitkar,“Verilog HDL-A Guide to Digital Design and Synthesis”, Pearson, 2003 • www.asic-world.com/verilog/vbehave3.html 22Prepared by Anand HD, Dr. AIT, Bengaluru
- 23.