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![2005 Verilog HDL 10 Function Examples Parity Generator module parity; reg [31:0] addr; reg parity; initial begin … end always @(addr) begin parity = calc_parity(addr); $display("Parity calculated = %b", calc_parity(addr) ); end function calc_parity; input [31:0] address; begin calc_parity = ^address; end endfunction endmodule](https://image.slidesharecdn.com/tasksandfunctions-140407012157-phpapp01/75/Verilog-Tasks-and-functions-10-2048.jpg)
![2005 Verilog HDL 16 module operation; parameter delay = 10; reg [15:0] A, B; reg [15:0] AB_AND, AB_OR, AB_XOR; initial $monitor( …); initial begin … end always @(A or B) begin bitwise_oper(AB_AND, AB_OR, AB_XOR, A, B); end task bitwise_oper; output [15:0] ab_and, ab_or, ab_xor; input [15:0] a, b; begin #delay ab_and = a & b; ab_or = a | b; ab_xor = a ^ b; end endtask endmodule Task Examples Use of input and output arguments](https://image.slidesharecdn.com/tasksandfunctions-140407012157-phpapp01/75/Verilog-Tasks-and-functions-16-2048.jpg)
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Verilog Tasks and functions
The document outlines the use of tasks and functions in Verilog HDL, emphasizing their purpose in behavioral modeling and code reuse. Functions return a single value without timing control, while tasks can have timing controls and multiple input/output arguments. Key differences and examples of their declaration and invocation are also provided.
Verilog Tasks and functions
- 1. Task and Functions VinChipSystems (A Design and Verification Company) Chennai
- 2. 2005 Verilog HDL2 Goal of presentation… Reusing code Tasks and Functions
- 3. 2005 Verilog HDL3 Introduction Procedures/Subroutines/Functions in SW programming languages The same functionality, in different places Verilog equivalence: Tasks and Functions Used in behavioral modeling
- 4. 2005 Verilog HDL4 Contents Functions Tasks Differences between tasks and functions
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- 6. 2005 Verilog HDL6 Functions Keyword: function, endfunction Can be used if the procedure does not have any timing control constructs returns exactly a single value has at least one input argument
- 7. 2005 Verilog HDL7 Functions (cont’d) Function Declaration and Invocation Declaration syntax: function <range_or_type> <func_name>; <input declaration(s)> <variable_declaration(s)> begin // if more than one statement needed <statements> end // if begin used endfunction
- 8. 2005 Verilog HDL8 Functions (cont’d) Function Declaration and Invocation Invocation syntax: <func_name> (<argument(s)>);
- 9. 2005 Verilog HDL9 Functions (cont’d) Semantics much like function in Pascal An internal implicit reg is declared inside the function with the same name The return value is specified by setting that implicit reg
- 10. 2005 Verilog HDL10 Function Examples Parity Generator module parity; reg [31:0] addr; reg parity; initial begin … end always @(addr) begin parity = calc_parity(addr); $display("Parity calculated = %b", calc_parity(addr) ); end function calc_parity; input [31:0] address; begin calc_parity = ^address; end endfunction endmodule
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- 12. 2005 Verilog HDL12 Tasks Keywords: task, endtask Must be used if the procedure has any timing control constructs zero or more than one output arguments May be on or more input arguments
- 13. 2005 Verilog HDL13 Tasks (cont’d) Task declaration and invocation Declaration syntax task <task_name>; <I/O declarations> <variable and event declarations> begin // if more than one statement needed <statement(s)> end // if begin used! endtask
- 14. 2005 Verilog HDL14 Tasks (cont’d) Task declaration and invocation Task invocation syntax <task_name>; <task_name> (<arguments>); input and inout arguments are passed into the task output and inout arguments are passed back to the invoking statement when task is completed
- 15. 2005 Verilog HDL15 Tasks (cont’d) I/O declaration in modules vs. tasks Both used keywords: input, output, inout In modules, represent ports connect to external signals In tasks, represent arguments pass values to and from the task
- 16. 2005 Verilog HDL16 module operation; parameter delay = 10; reg [15:0] A, B; reg [15:0] AB_AND, AB_OR, AB_XOR; initial $monitor( …); initial begin … end always @(A or B) begin bitwise_oper(AB_AND, AB_OR, AB_XOR, A, B); end task bitwise_oper; output [15:0] ab_and, ab_or, ab_xor; input [15:0] a, b; begin #delay ab_and = a & b; ab_or = a | b; ab_xor = a ^ b; end endtask endmodule Task Examples Use of input and output arguments
- 17. Tasks and Functions Differencesbetween Tasks and Functions
- 18. 2005 Verilog HDL18 Differences between... Functions Can enable (call) just another function (not task) Execute in 0 simulation time No timing control statements allowed At lease one input Return only a single value Tasks Can enable other tasks and functions May execute in non-zero simulation time May contain any timing control statements May have arbitrary input, output, or inout Do not return any value
- 19. 2005 Verilog HDL19 Differences between… (cont’d) Both are defined in a module are local to the module can have local variables (registers, but not nets) and events contain only behavioral statements do not contain initial or always statements are called from initial or always statements or other tasks or functions
- 20. 2005 Verilog HDL20 Differences between… (cont’d) Tasks can be used for common Verilog code Function are used when the common code is purely combinational executes in 0 simulation time provides exactly one output Functions are typically used for conversions and commonly used calculations
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