Verification of the QorIQ Communication Platform Containing CoreNet Fabric with SystemVerilog

Verification of the QorIQ Communication Platform Containing CoreNet Fabric with SystemVerilog

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  TM Freescale™ and theFreescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009 Verification of the QorIQ™ Communication Platform Containing CoreNet™ Fabric with SystemVerilog Sakar Jain & Robert Page Freescale Semiconductor Austin Texas
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  TMFreescale™ and theFreescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. 2 Agenda  Introduction  Verification Challenges  Verification Methodology  Verification IP  Conclusions  Q & A
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  TMFreescale™ and theFreescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. 3 Introduction  QorIQ™ (pronounced 'core eye-queue' ) Overview  Communication Processors for networking applications  Multi-core with tri-level cache hierarchy  Intended for combined control, data-path and application layer processing  Freescale processors based on Power Architecture ®(PA) technology  New CoreNet™ Interconnect on-chip fabric
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  TMFreescale™ and theFreescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. 4 QorIQ P4080 Communication Processor
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  TMFreescale™ and theFreescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. 5 CoreNet™ Platform Overview  CoreNet fabric sub-system is referred to as CoreNet Platform  CoreNet is an on-chip, high efficiency, high performance multiprocessor coherent interconnect  Point-to-point interconnect  Independent address and data paths  Pipelined address bus, split transactions, out-of-order completion .
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  TMFreescale™ and theFreescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. 6 CoreNet™ Coherency Fabric 1MB Front side L3 Cache 1MB Front side L3 Cache DDR2/3 Memory Controller DDR2/3 Memory Controller IO Bridge CoreNet Platform Block Diagram DUV CoreNet L3 Cache Power Architecture™ e500 Core 32KB D-Cache 32KB I-Cache 128KB Backside L2 Cache Core Complex Power Architecture™ e500 Core 32KB D-Cache 32KB I-Cache 128KB Backside L2 Cache Power Architecture™ e500 Core 32KB D-Cache 32KB I-Cache 128KB Backside L2 Cache IO Bridge IO Bridge Core Complex Core Complex
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  TMFreescale™ and theFreescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. 7 Agenda  QorIQ & CoreNet Platform Overview  Verification Challenges  Verification Methodology  Verification IP  Conclusions  Q & A
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  TMFreescale™ and theFreescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. 8 Verification Challenges  Multiple and new architectures to verify – CoreNet, Arbitration, Address Map, Security, Virtualization etc.  Extensive VIP development to support unit verification  New constrained random stimulus and associated coverage  Performance  Parameterized design to support multiple derivatives  Deal with legacy VIP  Adoption of new languages and tools (SV, SVA)
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  TMFreescale™ and theFreescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. 9 Agenda  QorIQ & CoreNet Platform Overview  Verification Challenges  Verification Methodology  Verification IP  Conclusions  Q & A
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  TMFreescale™ and theFreescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. 10 Verification Methodology  Top-down – black box to white box  Transaction Based Verification Methodology (TBVM)  Coverage driven  Extensive correctness checking  Hierarchical Verification  Reuse, reuse, reuse!
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  TMFreescale™ and theFreescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. 11 Agenda  QorIQ & CoreNet Platform Overview  Verification Challenges  Verification Methodology  Verification IP  Conclusions  Q & A
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  TMFreescale™ and theFreescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. 12 SystemVerilog Testbench  SystemVerilog Base Class Library (SVBCL)  Basic building blocks for constructing testbenches  Same concept as OVM or VMM libraries  SVBCL Extensions  Register randomization, randomization routines  Algorithmic and random stimulus base classes  Enhanced run-time parameter management  Address manager to manage address regions between masters  Data manager for intermediate and final results checking  Cache/Memory preloaders and checkers  Platform Verification IP  Extensive set of BFMs for CoreNet and all other IP protocols  Monitors, Assertions, Coverage  Random and directed stimulus
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  TMFreescale™ and theFreescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. 13 CoreNet VIP Overview  Object oriented model of all platform CoreNet-compliant units – Fabric, Proc Master, IO Bridges, Targets.  Includes BFMs, monitors, coverage and stimulus objects  Layered Architecture of BFMs  Stimulus Layer - higher level stimulus objects  Transaction Layer – implements transaction attributes of CoreNet  Link Layer – implements flow control aspects of CoreNet  Phy Layer – implements physical attributes of CoreNet protocol  BFMs model buffer resources, significant towards finding deadlock issues  Embedded coverage using SV covergroups  Multitude of control parameters (run-time) to modify behavior at run-time
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  TMFreescale™ and theFreescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. 14 How SV helped  OOP concepts – Abstraction, Inheritance & Polymorphism  Object-based randomization and constraints programming  Enhanced inter-process synchronization and communication mechanisms  Fine grain process control ( fork…join)  No memory leaks ( automatic garbage collection)  Enhanced tasks and functions  Interfaces ( parameterized, nested)  Powerful assertions & functional coverage capabilities
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  TMFreescale™ and theFreescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. 15 SV Gotchas  Constraint-solving  Unsupported constructs (e.g. parameterized classes)
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  TMFreescale™ and theFreescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. 16 CoreNet™ Coherency Fabric CoreNet™ Proc BFM CoreNet BFM Memory Target CoreNet BFM Memory Target CoreNet BFM IO Bridge CoreNet BFM IO Bridge CoreNet BFM IO Bridge DUV PA testcase SV Stim SV Stim SV Stim SV Stim CoreNet Monitors Corenet Fabric Testbench CoreNet™ Proc BFM CoreNet™ Proc BFM
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  TMFreescale™ and theFreescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. 17 CoreNet™ Fabric BFM CoreNet BFM AltMaster CoreNet BFM Memory Target CoreNet BFM Memory Target IO Bridge DUV PA testcase SV Stim SV Stim CoreNet BFM IO Bridge Testbench CoreNet BFM AltMaster CoreNet BFM AltMaster IP BFMs Monitor CoreNet Monitor CoreNet Monitor
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  TMFreescale™ and theFreescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. 18 CoreNet™ Coherency Fabric CoreNet Proc BFM 1MB Front side L3 Cache 1MB Front side L3 Cache IP BFM DDR2/3 Memory Controller DDR2/3 Memory Controller IO Bridge IP BFM CoreNet Platform Testbench DUV SV Stim or PA testcase SV Stim SV Stim CoreNet Monitors L3 Cache Power Architecture™ e500 Core 32KB D-Cache 32KB I-Cache 128KB Backside L2 Cache Core Complex Power Architecture™ e500 Core 32KB D-Cache 32KB I-Cache 128KB Backside L2 Cache CC Power Architecture™ e500 Core 32KB D-Cache 32KB I-Cache 128KB Backside L2 Cache CC PA testcase CoreNet BFM IoMaster/TargetIO Bridge
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  TMFreescale™ and theFreescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. 19 Agenda  QorIQ & CoreNet Platform Overview  Verification Challenges  Verification Methodology  Verification IP  Conclusions  Q & A
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  TMFreescale™ and theFreescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. 20 Successes  Successfully verified the entire CoreNet platform as an early adopter of System Verilog for testbenches.  Successfully applied advanced features of SV in creating a lean and efficient testbench with focus on reuse.  Reuse of CoreNet VIP for verification by cross-functional and cross-site teams.  Feature-rich testbench enabled early performance verification on RTL - helped flush out many performance bugs continued…
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  TMFreescale™ and theFreescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. 21 Successes  First Networking & Multimedia Group (NMG) SoC with fully integrated SV testbench  Sampled first silicon to customer in less than 3 weeks!  Customer is able to run 8-way MP software.  No major (show-stopper) functional CoreNet bugs in silicon  Lab Bugs/Verif Bugs = 0.7%  Found SV to be adequate for verifying complex designs.
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  TMFreescale™ and theFreescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. 22 Agenda  QorIQ & CoreNet Platform Overview  Verification Challenges  Verification Methodology  Verification IP  Conclusions  Q & A
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  TMFreescale™ and theFreescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. 23 Q & A