Mastering FPGA Design through Debug, Adrian Hernandez, Xilinx

Mastering FPGA Design through Debug Adrian Hernandez 21 May, 2010 Xilinx Confidential – Internal

Agenda  Introduction – Why is Debug important?  Incremental Design & Debug  System Integration  M Manufacturing and in the field test f t i d i th fi ld t t  Conclusion Page 2 © Copyright 2010 Xilinx

FPGA Debugging Challenges  Larger Devices enables more system integration – Drives up on-chip complexity – More clock domains on single FPGA – More 3rd party IP  High speed serial links now standard with FPGAs – Simplifies Chip-Chip signaling – Signal integrity issues complicated by multi-gigabit links – Serial protocol necessary for communication  Cost and Power Challenges – User applications demanding lower power – Cost sensitive solutions needed – Customers demanding more individualized features Page 4 © Copyright 2010 Xilinx

Debug Tools  Simulation – HDL Simulators – SPICE – Cycle accurate simulation models  On-Chip Instrumentation – Logic Analyzers – Input / Output drivers/monitors – Assertion monitors – Synthesized transaction generators and checkers  Off-Chip Instruments – Voltage Meters – Oscilloscopes – Logic Analyzers – Protocol Analyzers Page 5 © Copyright 2010 Xilinx

Design bugs originate from designs  Tools do not solve the debugging challenges  Root source of bugs is in the design  Use debug tools concurrently while designing – Design using controlled incremental changes – Verify, measure and analyze these changes – Build efficient and tight design and test iterations – Verify FPGA design in-circuit early and often Page 6 © Copyright 2010 Xilinx

IDD Fundamentals  Test driven design – Equal importance to test and design development – Design planning through test development – Perform upfront in circuit FPGA verification in-circuit  Add design changes incrementally – Learn from your mistakes – Take measured risks with smart code refactoring – Design exploration throughout development cycle Page 9 © Copyright 2010 Xilinx

Unit test and debug Functional behavior assertions  Document the core function of the module/entity – Plainly describe the unit’s function  Identify proper operation assertions – Create guide of correct transaction operation  Create test case definitions that drive assertions – Focus on triggering and validating assertions  Design in assertion verification – Use your language constructs to build in assertion checking – System Verilog assertion creation is not essential, but helpful y g , p Page 10 © Copyright 2010 Xilinx

Unit test and debug Unit testing on an FPGA g  Perform early testing on FPGA platforms  Unified simulation + hardware verification – Goal: Simulation matches hardware tests  Invest and reuse test infrastructure – Create reusable test components – Target test components for simulation AND hardware – Reuse test library to speed unit development – Build reusable test configurations Page 11 © Copyright 2010 Xilinx

Unit test and debug Experiment Analysis p y  Create custom GUI views to debug circuits  Save views and create basic unit screenshot documentation  Experiment with debug tools – Interactively confirm your design assertions – Use manual experiments to develop efficient regression tests Page 12 © Copyright 2010 Xilinx

Unit test and debug Regressions as debug aids g g  Use regression failures to analyze results – These failures should give clues where to find a bug  Incorporate regression analysis – Build analysis tools for test result processing  Incorporate regressions into your check-in process – Use unit regressions often – Exercising regressions is part of check-in process Page 13 © Copyright 2010 Xilinx

Unit test and debug FPGAs based regressions g  Unit design must target an FPGA – Identify an FPGA to target – Use a development boards for pre-proto testing  Have at least one test execute in hardware – Unit design will run in-circuit independent of the system  Strive to emulate simulation verification in-circuit – Simulation should not exclude developing a hardware testing  FPGA regressions run at check-in – Unit design should always synthesize g y y – Unit design should always implement on target FPGA Page 14 © Copyright 2010 Xilinx

Refactor  Clean up code and variables for maintainability  Optimize for power/performance goals  Take measured risks – Try new solutions verify with unit tests solutions, – Experiment “breakthrough” ideas throughout the design cycle  Refactor the unit design often – Strive to always have the new code better than the original Page 15 © Copyright 2010 Xilinx

Incremental Design & Debug  IDD Fundamentals – Plan for success with tested incremental changes  Unit test and debug – Designing for high quality and low maintenance  Code refactoring – Plan for design breakthroughs! Page 16 © Copyright 2010 Xilinx

System Integration Building on IP g  Always build on known good IP – Unit testing ensures good IP – Use only trusted 3rd party IP  Assume IP has been tested – Assume that checked-in IP was fully tested – Assume 3rd party was fully verified  System design is all about IP block connections – Wiring is all that should be at the system level – Complex functions exist in sub-units – Avoid adding “quick-fixes” at the system level Page 19 © Copyright 2010 Xilinx

System Integration Focus on IP interface  Debug and verification of interfaces – Focus is not on the verification of the IP blocks  Concentrate on transaction level operations  Only verify basic IP functional correctness – Treat IP as a black box function processor  Cover extreme system cases for system level metrics – Power measurement – Clock jitter – Signal integrity g g y Page 20 © Copyright 2010 Xilinx

System Integration Use unit test harness  Fix unit tests – Interface verification may occasionally find unit bugs – Unit tests should be updated to catch bugs found  3rd party IP may require separate unit test – 3rd party IP bugs should have separate unit tests – Unit tests are used for fixes or workarounds from vendor  Reuse unit level infrastructure for deeper IP block debugging – Debug unit bugs by using the unit tests – Don’t debug unit issues at the infrastructure Page 21 © Copyright 2010 Xilinx

System Integration System + FPGA y  Create an efficient system simulation environment  Use FPGAs to get accurate system results  Build in-circuit system level regression tests Page 22 © Copyright 2010 Xilinx

System Integration : Simulation + FPGA Simulation Environment  Use transaction verification methods / tools (ex OVM)  Simulate basic and random scenarios  Use simulation to experiment special conditions – Ex: Cross clock domain crossing – Ex: Min/Max conditions  Have "experimentation-ready" setups – Create configurations for running in-circuit scenarios in simulation Page 23 © Copyright 2010 Xilinx

System Integration : Simulation + FPGA In-circuit Verification  Verify on prototype board – Reproduce bus transactions similar to simulation – Create system DFT blocks – Use test tools scripting to build system regression tests  Measure and analyze design margins – Manually measure the design margins – Create test harness that allows you to run in-circuit regressions Page 24 © Copyright 2010 Xilinx

System Integration : Simulation + FPGA Regression testing g g  Build regression on FPGA reconfiguration – Create multiple designs to validate sections the system – Accelerate long simulation tests by running in-circuit  Turn your experiments to regression tests – Seek to turn system measurement and analysis into regressions  Run your system level test regularly – Use board farms to help run parallel in-circuit tests – Build test frameworks for easy addition of in-circuit tests Page 25 © Copyright 2010 Xilinx

System Integration Learn from mistakes  Extend testing to cover bugs found  Update specifications to reflect actual implementation  Share your IP, share your wisdom! – Encourage reuse across projects and teams – Have open discussions on lessons learned Page 26 © Copyright 2010 Xilinx

System Integration  Build on known good IP – IP blocks design strives to be ready for system integration  Focus on the IP interface – System integration main goal is to join IP blocks  Use unit test harness – Enables faster debug and more “what if” exploration  Simulation + FPGA – Transaction methods simplifies and accelerates verification – In-circuit verification improves q p quality and speed regression testing y p g g  Learn from mistakes – Always improve the design and your knowledge Page 27 © Copyright 2010 Xilinx

Manufacturing and in-the-field test Manufacturing success g  Create multiple designs for fast board verification – Non-scan based verification running at speed – Covers more than connectivity faults  Validate high speed serial links independently – Ex: serial exercisers like Xilinx IBERT – Use protocol based reference designs re-targeted for your board  Verify system connectivity – Test memory interfaces with specialized IP/SW exercisers – Test bus connectivity through basic bus exercisers  Perform quick measurements for accurate margin analysis – Ensures high quality for customers – Catch performance issues from multi source part vendors multi-source Page 29 © Copyright 2010 Xilinx

Manufacturing and in-the-field test Lower support costs pp  Convert manufacturing tests to in-the-field tests  Use special test modes to load verification FPGA bits  Incorporate return codes into customer support guide  D i Design feedback into in-the-field support f db k i t i th fi ld t – Use test results to improve verification – Regularly meet with product support – Seek to reduce support cost Page 30 © Copyright 2010 Xilinx

Conclusion  Build on FPGA reconfiguration – Keep the customer happy – No regressions! Always improve the product! – Add features in incremental steps use IDD to the fullest steps, Page 33 © Copyright 2010 Xilinx

Conclusion  Build on FPGA reconfiguration  Take advantage of in-circuit test – Use on chip debug tools for in-circuit test – Extend create and reuse your in-circuit tools Extend, in circuit – Incorporate regressions into product Page 34 © Copyright 2010 Xilinx

Conclusion  Build on FPGA reconfiguration  Take advantage of in-circuit test  Seek design perfection, seek design simplicity Any intelligent fool can make things bigger more complex and more bigger, violent. It takes a touch of genius and a lot of courage to move in the opposite direction. —Albert Einstein Page 35 © Copyright 2010 Xilinx

Conclusion  Build on FPGA reconfiguration  Take advantage of in-circuit test  Seek design perfection, seek design simplicity  Ab beautiful mind tif l i d – Reuse and share your debug and testing IP – Share your knowledge and experiences Page 36 © Copyright 2010 Xilinx

Conclusion  Build on FPGA reconfiguration  Take advantage of in-circuit test  Seek design perfection, seek design simplicity  Ab beautiful mind tif l i d – Reuse and share your debug and testing IP – Share your knowledge and experiences Buddhist Saying: “To know and not to use is not yet to kno ” kno se et know” Page 37 © Copyright 2010 Xilinx

References:  Xilinx market solutions development IP and boards – http://www.xilinx.com/esp  Xilinx ChipScope Analyzer – http://www xilinx com/chipscope http://www.xilinx.com/chipscope  OVM – http://www.ovmworld.org  Agilent – http://www.agilent.com/find/9000 Page 39 © Copyright 2010 Xilinx

Mastering FPGA Design through Debug, Adrian Hernandez, Xilinx

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Mastering FPGA Design through Debug, Adrian Hernandez, Xilinx