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DESIGN CHOICES FOR EMBEDDED REAL-TIME CONTROL SYSTEMS @ 4th FPGA Camp
The document discusses design choices for embedded real-time control systems using FPGA technology, highlighting the evolution from hardware-centric to software-centric design flows. It covers issues such as I/O connectivity, parallel processing, and the integration of processing solutions like the Zynq-7000 extensible processing platform. Additionally, it addresses challenges related to scalability, reliability, and system partitioning in control applications.
DESIGN CHOICES FOR EMBEDDED REAL-TIME CONTROL SYSTEMS @ 4th FPGA Camp
- 1. Design Choices forEmbedded Real-Time Control SystemsFPGA Camp, April 6, 2011Endric Schubert, Missing Link ElectronicsGlenn Steiner, Xilinx4/6/20111FPGA Camp 2011
- 2. Real-Time Closed-Loop ControlSystems4/6/20112FPGA Camp 2011
- 3. Embedded Real-Time ControlSystems- A Quadruple WhammyWide variety of I/OProcessing in Real-TimeSafety RegulationsDevice Obsolescence4/6/2011FPGA Camp 20113
- 4. Processing Steps inReal-Time Control Systems4/6/20114FPGA Camp 2011An I/O connectivity problemProcessing problemCustomization problemProcessing problemReliability problemAnother I/O Connectivity problem
- 5. Real-Time Processing ona MicrocontrollerLike packet / video streaming … BUT: must not loose any data!4/6/2011FPGA Camp 20115
- 6. Scalability Problems inMulti-Channel Systems4/6/20116FPGA Camp 2011
- 7. Von Neumann Needsa Companion!Sequential Processing with CPUC, C++ ProgramParallel Processing with Logic GatesVHDL, Verilog "Program"4/6/2011FPGA Camp 20117Courtesy: Dr. Andre DeHon, UPenn
- 8. Proposal: FPGA-Based Real-TimeControl System4/6/20118FPGA Camp 2011How to do:I/O connectivity (read sensors, drive actuators)Signal conditioningClosed-loop control
- 9. FPGA I/O Interfaces& Communication PeripheralsCovers almost all relevant I/O standardsAnd CommunicationInterfaces4/6/20119FPGA Camp 2011
- 10. FPGA-Based Signal Conditioning4/6/201110FPGACamp 2011Today: Digital Signal ProcessingOld School: Analog
- 11. Closed-Loop PID Control4/6/201111FPGACamp 2011Courtesy: Dr. GiulioCorradi, Xilinx
- 12. PID Control inan FPGADelay OptimizedArea Optimized4/6/2011FPGA Camp 201112Zhao et al.: FPGA Implementation of Closed-Loop Control System for Small Scale Robot, IEEE, July 2005
- 13. Scale-up Multi-Channel Controlwith Parallel Processing in the FPGA4/6/201113FPGA Camp 2011
- 14. The Need toRun (Sequential) Software4/6/201114FPGA Camp 2011
- 15. History Lesson: FPGAsContinue to Evolve to Meet Processing System RequirementsCo-processingEmbeddedProcessingComplexControlIncreasing FPGA CapabilityProcessors tightly coupled to FPGA fabricenable extendibility with co-processing to meet real-time system requirements ControlLogicGlueLogic201119851990199520004/6/201115FPGA Camp 2011
- 16. Yesterday’s FPGA DesignsHardware-CentricDesign Flow With FPGAs4/6/2011FPGA Camp 201116
- 17. It's the Software,Dude!Embedded Processing TodaySoftware-Centric Design Flow With FPGAs4/6/2011FPGA Camp 201117
- 18. FPGA-to-CPU ConnectivityCompanion ChipsIntegratedSolutions"A symbiosis of CPU and FPGA on one die to reduce cost and PCB space!"4/6/201118FPGA Camp 2011
- 19. A Convergence ofProcessing SolutionsGeneral PurposeProcessorsFPGA SoftProcessorsASSPProcessorsFPGA HardProcessors4/6/201119FPGA Camp 2011
- 20. A Convergence ofProcessing SolutionsExtensibleProcessingPlatformGeneral PurposeProcessorsFPGA SoftProcessorsMemoryInterfaces7 SeriesProgrammableLogic ProcessingSystemCommonPeripheralsCommon PeripheralsCustomPeripheralsARM®Dual Cortex-A9 MPCore™ SystemCommon AcceleratorsCustom AcceleratorsASSPProcessorsFPGA HardProcessors4/6/201120FPGA Camp 2011
- 21. Zynq-7000 Extensible ProcessingPlatformComplete ARM®-based Processing System
- 22. Dual ARM Cortex™-A9MPCore™, processor centric
- 23. Integrated memory controllers& peripherals
- 24. Fully autonomous tothe Programmable Logic
- 25.
- 26. Used to extendProcessing System
- 27. Scalable density andperformance
- 28. Over 3000 internalinterconnects
- 29.
- 30. Wide range ofexternal multi-standard I/O
- 31. High performance integratedserial tranceivers
- 32. Analog-to-Digital Converter inputsMemoryInterfaces7SeriesProgrammableLogic ProcessingSystemCommonPeripheralsCommon PeripheralsCustomPeripheralsARM®Dual Cortex-A9 MPCore™ SystemCommon AcceleratorsCustom AcceleratorsSoftware & Hardware Programmable4/6/201121FPGA Camp 2011
- 33. Zynq-7000 Extensible ProcessingSystemProcessing SystemDynamic Memory ControllerDDR3, DDR2, LPDDR2Static Memory ControllerQuad-SPI, NAND, NORProgrammableLogic:System Gates,DSP, RAMAMBA® SwitchesAMBA® Switches2x SPIARM® CoreSight™ Multi-core & Trace Debug2x I2CNEON™/ FPU EngineNEON™/ FPU Engine2x CANCortex™-A9 MPCore™32/32 KB I/D Caches2x UARTCortex™-A9 MPCore™32/32 KB I/D CachesMIOI/OMUXGPIO512 KB L2 CacheSnoop Control Unit (SCU)Multi-Standards I/Os (3.3V & High Speed 1.8V)ACP2x SDIOwith DMATimer Counters256 KB On-Chip MemoryDMAGeneral Interrupt ControllerConfiguration2x USBwith DMA2x GigEwith DMAAMBA® SwitchesAMBA® SwitchesPCIeAMSMulti-Standards I/Os (3.3V & High Speed 1.8V)Multi Gigabit Transceivers4/6/201122FPGA Camp 2011
- 34. Zynq-7000 EPP ProcessorsProcessingSystemDynamic Memory ControllerDDR3, DDR2, LPDDR2Static Memory ControllerQuad-SPI, NAND, NORProgrammableLogic:System Gates,DSP, RAMAMBA® SwitchesAMBA® Switches2x SPIARM® CoreSight™ Multi-core & Trace Debug2x I2CNEON™/ FPU EngineNEON™/ FPU Engine2x CANCortex™-A9 MPCore™32/32 KB I/D Caches2x UARTCortex™-A9 MPCore™32/32 KB I/D CachesMIOI/OMUXGPIO512 KB L2 CacheSnoop Control Unit (SCU)Multi-Standards I/Os (3.3V & High Speed 1.8V)ACP2x SDIOwith DMATimer Counters256 KB On-Chip MemoryDMAGeneral Interrupt ControllerConfiguration2x USBwith DMA2x GigEwith DMAAMBA® SwitchesAMBA® SwitchesPCIeAMSMulti-Standards I/Os (3.3V & High Speed 1.8V)Multi Gigabit Transceivers4/6/201123FPGA Camp 2011
- 35. Zynq-7000 EPP MemoryInterfaces Processing SystemDynamic Memory ControllerDDR3, DDR2, LPDDR2Static Memory ControllerQuad-SPI, NAND, NORProgrammableLogic:System Gates,DSP, RAMAMBA® SwitchesAMBA® Switches2x SPIARM® CoreSight™ Multi-core & Trace Debug2x I2CNEON™/ FPU EngineNEON™/ FPU Engine2x CANCortex™-A9 MPCore™32/32 KB I/D Caches2x UARTCortex™-A9 MPCore™32/32 KB I/D CachesMIOI/OMUXGPIO512 KB L2 CacheSnoop Control Unit (SCU)Multi-Standards I/Os (3.3V & High Speed 1.8V)ACP2x SDIOwith DMATimer Counters256 KB On-Chip MemoryDMAGeneral Interrupt ControllerConfiguration2x USBwith DMA2x GigEwith DMAAMBA® SwitchesAMBA® SwitchesPCIeAMSMulti-Standards I/Os (3.3V & High Speed 1.8V)Multi Gigabit Transceivers4/6/201124FPGA Camp 2011
- 36. I/O Connectivity inZynq-7000 EPPProcessing SystemDynamic Memory ControllerDDR3, DDR2, LPDDR2Static Memory ControllerQuad-SPI, NAND, NORProgrammableLogic:System Gates,DSP, RAMAMBA® SwitchesAMBA® Switches2x SPIARM® CoreSight™ Multi-core & Trace Debug2x I2CNEON™/ FPU EngineNEON™/ FPU Engine2x CANCortex™-A9 MPCore™32/32 KB I/D Caches2x UARTCortex™-A9 MPCore™32/32 KB I/D CachesMIOI/OMUXGPIO512 KB L2 CacheSnoop Control Unit (SCU)Multi-Standards I/Os (3.3V & High Speed 1.8V)ACP2x SDIOwith DMATimer Counters256 KB On-Chip MemoryDMAGeneral Interrupt ControllerConfiguration2x USBwith DMA2x GigEwith DMAAMBA® SwitchesAMBA® SwitchesPCIeAMSMulti-Standards I/Os (3.3V & High Speed 1.8V)Multi Gigabit Transceivers4/6/201125FPGA Camp 2011
- 37. Agile Mixed Signal(AMS) for Data AcquisitionProcessing SystemDynamic Memory ControllerDDR3, DDR2, LPDDR2Static Memory ControllerQuad-SPI, NAND, NORProgrammableLogic:System Gates,DSP, RAMAMBA® SwitchesAMBA® Switches2x SPIARM® CoreSight™ Multi-core & Trace Debug2x I2CNEON™/ FPU EngineNEON™/ FPU Engine2x CANCortex™-A9 MPCore™32/32 KB I/D Caches2x UARTCortex™-A9 MPCore™32/32 KB I/D CachesMIOI/OMUXGPIO512 KB L2 CacheSnoop Control Unit (SCU)Multi-Standards I/Os (3.3V & High Speed 1.8V)ACP2x SDIOwith DMATimer Counters256 KB On-Chip MemoryDMAGeneral Interrupt ControllerConfiguration2x USBwith DMA2x GigEwith DMAAMBA® SwitchesAMBA® SwitchesPCIeAMSMulti-Standards I/Os (3.3V & High Speed 1.8V)Multi Gigabit Transceivers4/6/201126FPGA Camp 2011
- 38. Agile Mixed Signal(AMS) ProcessingDual 12-bit 1 Msps Analog-to-Digital Converters
- 39. ADCs carry outa 16-bit resolution conversion
- 40. Factory tested andspecified 12-bit accuracy with 1V input range
- 41. Built in digitalgain and offset correction / calibration
- 42. Dual Independent Track& Hold (T/H) Amplifiers
- 43. Separate Track/Hold amplifierensures maximum throughput using multiplexed analog input channels
- 44.
- 45. External reference inputoption
- 46. On-Chip Thermal andSupply Sensors
- 47. Flexible External AnalogInputs
- 48. Differential analog inputswith high common mode noise rejection
- 49. Support for unipolar,bipolar, and true differential input signal types 4/6/201127FPGA Camp 2011
- 50. On-Chip and ExternalEnvironmental MonitoringMonitoring for higher reliability in industrial applicationsFactory tested on-chip monitoringEasier to implement than external solutionse.g., thermal diode monitorCounter measures against physical attack / tampering in A&DUS government mandate: Cryptographic model must have built in counter measures against manipulation of power supplies and operating temperaturesProtection against reverse engineering and IP theftDiagnostics for HW design and verificationEasy to use JTAG access with ChipScope supportEspecially difficult to access places e.g., in enclosures / cabinetsJTAG4/6/201128FPGA Camp 2011
- 51. Integrating It AllTogether:An Industrial Motor Control Application4/6/201129FPGA Camp 2011
- 52. Put the BurdenWhere it Fits Best!Extensible Processing PlatformsAllow optimum system partitioning between software and hardwareBuild configurable systems that match your application!4/6/2011FPGA Camp 2011Page 30
- 53. Modern Implementation4/6/201131FPGA Camp2011Extensible Processing PlatformMemoryInterfaces7 SeriesProgrammableLogic ProcessingSystemCommonPeripheralsCommon PeripheralsCustomPeripheralsARM®Dual Cortex-A9 MPCore™ SystemCommon AcceleratorsCustom Accelerators