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CPU Architecture - Advanced
The document discusses advanced CPU architecture. It describes the von Neumann architecture which uses a single processor for program control and follows a fetch-decode-execute-store cycle to process instructions one at a time in a linear sequence from memory. It also describes the differences between CISC (Complex Instruction Set Computer) and RISC (Reduced Instruction Set Computer), with CISC having more complex instructions that can perform tasks in one cycle while RISC uses simpler instructions that may require multiple cycles to complete complex tasks. An example is provided to illustrate how a RISC would take more cycles than a CISC to compute an average.
CPU Architecture - Advanced
- 1. CPU Architecture - Advanced YongHeui Cho @ Mokwon University Some of slides are referred to: [1] 3.3 Computer Architectures, slideshare.
- 2. Basic Computer Design 5.Sequential Logic Circuit 6. CPU Architecture - Basic 7. CPU Architecture - Advanced 8. ARM CPU
- 3. Simplified Architecture 3□ Courtesyto The CPU, slideshare. IR data Control Unit (CU) ALU
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- 5. Features • Data andinstructions can be stored in the same memory. • It uses a single processor for program control. • Cycle: fetch-decode-execute-store • Execution performs the instruction at a time in a linear sequence. 5□ Courtesy to 3.3 Computer Architectures, slideshare, slideshare.
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- 8. CISC • Complex InstructionSet Computer • CISC has more complex instructions available to it thus it may be able to perform the task in just one cycle (by using one of its complex operations available) – Large number of instructions available 8□ Courtesy to 3.3 Computer Architectures, slideshare, slideshare.
- 9. CISC of Intel 9 •PCs, servers → mobile devices
- 10. RISC • Reduced InstructionSet Computer • RISC only has a simple instruction set thus to perform a complex task it may take several ‘cycles’ of basic instructions. – Limited number of instructions available 10□ Courtesy to 3.3 Computer Architectures, slideshare, slideshare.
- 11. RISC of ARM •Mobile devices → PCs, servers 11
- 12. Example of CISC/RISC 12 ARISC might have the operations: • ADD • SUB • DIV • etc A CISC might have the operations: • ADD • SUB • DIV • AVR (average) • etc Task: find the average! □ Courtesy to 3.3 Computer Architectures, slideshare, slideshare.