ASIC Implementation of Triple Data Encryption Algorithm (3DES)

ASIC Implementation of Triple Data Encryption Algorithm (3DES)

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  Triple DES Team members:Junjie Wang, Xiao Xiao, Zhuofan Li, Ming Huen Lee 1
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  Overview - Whatis 3DES? Users are able encrypt / decrypt data in a secure way Prevent hacking into important data Algorithm applies Data Encryption Standard (DES) 3 times Ciphertext = EK3(DK2(EK1(plaintext))) Each DES has 16 rounds of processing -> Encrypted with 56-bit key Appropriate for ASIC design Less time delay Consume less power Data will send through avalon bus to the FPGA 2
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  System Design 3
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  Operation Flow Chart 4
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  System Architecture 5
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  Fixed Success Criteria 1.Test benches exist for all top level components and the entire design. The test benches for the entire design can be demonstrated or documented to cover all of the functional requirements given in the design specific success criteria. (2 pts/Achieved) 2. Entire design synthesizes completely, without any inferred latches, timing arcs, and, sensitivity list warnings (4 pts/Achieved) 3. Source and mapped version of the complete design behave the same for all test cases. The mapped version simulates without timing errors except at time zero (2 pts/Achieved) 4. A complete IC layout is produced that passes all geometry and connectivity checks (2 pts) 5. The entire design complies with targets for area, pin count, throughput (if applicable), and clock rate. (2pts) 6
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  Fixed Criteria 1& 2 7
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  Fixed Criteria 3 8
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  Fixed Criteria 4 9
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  Fixed Criteria 5 10
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  Design Specific SuccessCriteria 1. Demonstrate by utilizing a know, working 3DES online tool that the output of the design both encrypts and decrypts according to the 3DES algorithm. (1 point/Achieved) 2. Demonstrate by simulation of verilog test benches that the complete design is able to utilize pipelining.(1 point/Achieved) 3. Demonstrate by simulation of verilog test benches that the complete design is able to successfully implement 3DES encryption (2 points/Achieved) 4. Demonstrate by simulation of verilog test benches that the complete design is able to successfully implement 3DES decryption. (2 points/Achieved) 5. Demonstrate that the complete design is able to dump data from atom to FPGA using C code for Avalon-Bus. (2 points/Achieved) 11
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  Design Specific SuccessCriteria #1 2a 8d 69 de 9d 5f df f9 bd 0a ac 78 21 19 7f a4 Message Key Output 12
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  Design Specific SuccessCriteria #2 New data input every 8 clock cycles when dataready is high 13
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  Design Specific SuccessCriteria #2 cont. Apply Triple DES algorithm using pipelining with same keys Input data 1 Input data 2 Encrypted data 1 Encrypted data 2 Encrypted data 1 Encrypted data 2 Decrypted data 1 Decrypted data 2 14
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  Design Specific SuccessCriteria #3,4 Encryption & Decryption using three different keys. Input data Encrypted data Encrypted data Original data 15
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  Design Specific SuccessCriteria #5 Output Input Next_enable 16
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  Quartus Report Area onthe FPGA FPGA CLOCK 17
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  Conclusion Challenges: Develop an efficientalgorithm for pipelining process FPGA (communication with atom) Time Management Approaches differently: Use the SDRAM on the FPGA Improvement: Expand the key size of the Triple DES to make it more secure 18
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  Appendix: One Roundof Processing in DES 19
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  Appendix: One Roundof Processing in DES 20
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  Appendix: 16 RoundsDES 21
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  Appendix: 16 RoundsDES 22
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  Appendix: Key ScheduleAlgorithm (KSA) 23