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Simulation using model sim
This document provides an overview of using ModelSim to simulate VHDL designs. It discusses compiling and simulating designs from the command line as well as interactively within ModelSim. Key steps covered include compiling VHDL files with vcom, simulating with vsim, adding signals to the waveform window, applying inputs, running simulations, generating makefiles, and creating and simulating designs within the ModelSim GUI. The document aims to teach basic ModelSim simulation commands and workflow.
Simulation using model sim
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- 2. CopyrightsCopyright © 2010to authors. All rights reservedAll content in this presentation, including charts, data, artwork and logos (from here on, "the Content"), is the property of Amr Ali or the corresponding owners, depending on the circumstances of publication, and is protected by national and international copyright laws.Authors are not personally liable for your usage of the Content that entailed casual or indirect destruction of anything or actions entailed to information profit loss or other losses.Users are granted to access, display, download and print portions of this presentation, solely for their own personal non-commercial use, provided that all proprietary notices are kept intact. Product names and trademarks mentioned in this presentation belong to their respective owners.VHDL 360 ©2
- 3. ObjectiveUsing ModelSim tocompile and simulate a given design unitSkills gained:Identify basic Simulator commandsVHDL 360 ©3
- 4. OutlineCommand Line SimulationCompileand SimulateAdd Signals to WaveApplying InputsInteractive SimulationVHDL 360 ©4
- 5. Command Line SimulationMakesure Modelsim exists in the path by doing the followingWindows:Start run -> cmdIn cmd window:vsim -versionLinux:In any shell:vsim -versionVHDL 360 ©5
- 6. Command Line SimulationCreateVHDL fileEdit the file my_demo1.vhdInsert the text and saveVHDL 360 ©6LIBRARYieee;USEieee.std_logic_1164.all;ENTITYandgateISport(a, b:instd_logic_vector(2downto0); c:outstd_logic_vector(2downto0));ENDENTITY;ARCHITECTUREbehavOFandgateISBEGIN c <= a and b;ENDARCHITECTURE;
- 7. Compile and Simulatevlibworkvcom <VHDL files> vsim <top level>VHDL 360 ©7vlib: creates a library to compile and simulate the code with
- 8. vcom: compiles VHDLfiles, the files should be ordered in a hierarchal way [leaf level first then top]
- 9. vsim: starts thesimulator to simulate the top level moduleAdd signals to WaveRMB on any signal in the Objects window Add to Wave signals in RegionNow start applying inputs and monitor outputsVHDL 360 ©8
- 10. Applying InputsRMB oninput port forceVHDL 360 ©9In the “value” field, insert an appropriate value OK
- 11. Apply inputs toother inputsRun SimulationPress run buttonMonitor the outputVHDL 360 ©10
- 12. Make FilesOn Unix:Ifyou changed the code you will have to recompile the design files again.A make file is used to do repetitive compilation and simulation tasks; “Make” knows which files have been edited and automatically compiles only changed files.ModelSim offers a simple way to automatically generate a Makefile for your design hierarchy.vmake work > MakefileTo recompile code at anytime just type makeVHDL 360 ©11
- 13. Interactive SimulationFile new projectInsert project name and location; leave other fields with defaultsVHDL 360 ©12
- 14. Interactive SimulationIn “Additems to the project” window choose “Create new file”Insert file nameMake sure to select VHDLVHDL 360 ©13
- 15. Interactive SimulationCreate VHDLfileEdit the file my_demo1.vhdInsert the text and saveVHDL 360 ©14LIBRARYieee;USEieee.std_logic_1164.all;ENTITYandgateISport(a, b:instd_logic_vector(2downto0); c:outstd_logic_vector(2downto0));ENDENTITY;ARCHITECTUREbehavOFandgateISBEGIN c <= a and b;ENDARCHITECTURE;
- 16. Compile VHDL filesSelectthe file RMB compile selectedVHDL 360 ©15
- 17. SimulationSimulate menu Start SimulationExpand work library and select andgateOKVHDL 360 ©16
- 18. ContactsYou can contactus at:http://www.embedded-tips.blogspot.com/VHDL 360 ©17