Low power ldpc decoder implementation using layer decoding

Low power ldpc decoder implementation using layer decoding

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  LOW-POWER LDPC DECODER IMPLEMENTATIONUSING LAYER DECODING AJITH.C 212111419001 Guide BY M.E VLSI Design Mr.P Kabilamani,Lecturer,ECE
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  Abstract  Method forcreating LDPC codes which are specifically designed to be hardware friendly.  Layer decoding is the one of the efficient approach to decode the LDPC code with good error rate performance.  Proposed approach will efficiently decrease the power.
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  INTRODUCTION  LDPC Codeis a Linear Error Correcting Code.  LDPC codes are finding increasing use ◦ 1. reliable and highly efficient information transfer over bandwidth ◦ 2. return channel–constrained links in the presence of data-corrupting noise.  Error correcting code in the new DVB-S2
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  Cont…  Representations forLDPC Codes Matrix and Graphical Representations
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  Existing Method  LayeredDecoding
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  Cont…  Most PracticalLDPC Codes are structured to support layered decoders in hardware.  This concept is usually generalized by dividing the H-Matrix into Layers.  Only one CN can access a given VN memory at a specific time.  In a layered decoder,one CN processor can be designed to serially process the different rows of the H-Matrix.
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  Proposed Method  VectoredLayer Decoding
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  Cont…  Vector DecoderArchitecture overcomes the limitation of the layered decoder by packing multiple messages in the same memory unit.  Throughput of a vector decoder can be times that of a scalar decoder.
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  Phase I  LDPCEncoding
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  Phase II  LDPCDecoding using Layer Decoding.  Vectored Layer Decoding.
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  LDPC Encoding  GeneratorMatrix from Parity Check Matrix.  Encoding Technique.
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  Generator Matrix fromParity Check Matrix  Parity Check Matrix(H) H(qxn)=[Pqxk : Iq ].  Generator Matrix(G) G(kxn) =[Ik:Pkxq].
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  Encoding Technique  Encodingby Matrix Multiplication  Systematic codeword Generation codeword,X=axGT a=(a1,a2,……ak),k information bits to be encoded. GT=Generator Matrix Transpose
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  Software Used  Simulation: Xilinx ISE 9.1i
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  Simulation For HMatrix To G Matrix Generation
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  Cont..
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  Simulation For LDPC Encoding
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  References  R. Gallager,“Low-density parity-check codes,” IEEE Trans. Inf. Theory, vol. IT-8, no. 1, pp. 21– 28, Jan. 1962.  Z. Li, L. Chen, L. Zeng, S. Lin, and W. Fong, “Efficient encoding of quasi-cyclic low- density parity-check codes,” IEEE Trans. Commun.,vol. 53, no. 11, p. 1973, Nov. 2005.  E. Yeo, P. Pakzad, B. Nikolic, and V. Anantharam, “High throughput low-density parity- check decoder architectures,” in Proc. IEEE Global Telecommun. Conf., 2001, vol. 5, pp. 3019–3024.
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  THANK YOU