8051 Microcontroller architecture and operation

 The microprocessor is the core of computer systems.  Nowadays many communication, digital entertainment, portable devices, are controlled by them.  A designer should know what types of components he needs, ways to reduce production costs and product reliable.

DIFFERENT ASPECTS OF A MICROPROCESSOR/CONTROLLER  Hardware :Interface to the real world  Software :order how to deal with inputs

 CPU: Central Processing Unit  I/O: Input /Output  Bus: Address bus & Data bus  Memory: RAM & ROM  Timer  Interrupt  Serial Port  Parallel Port

CPU General- Purpose Micro- processor RAM ROM I/O Port Timer Serial COM Port Data Bus Address Bus General-Purpose Microprocessor System  CPU for Computers  No RAM, ROM, I/O on CPU chip itself  Example ： Intel’s x86, Motorola’s 680x0 Many chips on mother’s board General-purpose microprocessor

RAM ROM I/O Port Timer Serial COM Port Microcontroller CPU  A smaller computer  On-chip RAM, ROM, I/O ports...  Example ： Motorola’s 6811, Intel’s 8051, Zilog’s Z8 and PIC 16X A single chip Microcontroller

Microprocessor  CPU is stand-alone, RAM, ROM, I/O, timer are separate  designer can decide on the amount of ROM, RAM and I/O ports.  expansive  versatility  general-purpose Microcontroller • CPU, RAM, ROM, I/O and timer are all on a single chip • fix amount of on-chip ROM, RAM, I/O ports • for applications in which cost, power and space are critical • single-purpose Microprocessor vs. Microcontroller

 Embedded system means the processor is embedded into that application.  An embedded product uses a microprocessor or microcontroller to do one task only.  In an embedded system, there is only one application software that is typically burned into ROM.  Example ： printer, keyboard, video game player Embedded System

1. meeting the computing needs of the task efficiently and cost effectively • speed, the amount of ROM and RAM, the number of I/O ports and timers, size, packaging, power consumption • easy to upgrade • cost per unit 2. availability of software development tools • assemblers, debuggers, C compilers, emulator, simulator, technical support 3. wide availability and reliable sources of the microcontrollers. Three criteria in Choosing a Microcontroller

Intel introduced 8051, referred as MCS-51, in 1981  The 8051 is an 8-bit processor  The CPU can work on only 8 bits of data at a time  The 8051 had 128 bytes of RAM  4K bytes of on-chip ROM  Two timers  One serial port  Four I/O ports, each 8 bits wide  6 interrupt sources

There are 128 bytes of RAM in the 8051  Assigned addresses 00 to 7FH The 128 bytes are divided into three different groups as follows: 1) A total of 32 bytes from locations 00 to 1F hex are set aside for register banks and the stack 2) A total of 16 bytes from locations 20H to 2FH are set aside for bit-addressable read/write memory 3) A total of 80 bytes from locations 30H to 7FH are used for read and write storage, called scratch pad

 The stack is a section of RAM used by the CPU to store information temporarily  The register used to access the stack is called the SP (stack pointer) register  The storing of a CPU register in the stack is called a PUSH  Loading the contents of the stack back into a CPU register is called a POP  The CPU also uses the stack to save the address of the instruction just below the CALL instruction

 SFRs provide control and data exchange with the microcontroller’s resources and peripherals  Registers which have their byte addresses ending with 0H or 8H are byte- as well as bit- addressable  Some registers are not bit- addressable. These include the stack pointer (SP) and data pointer register (DPTR)

Pin Description of the 8051 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RST (RXD)P3.0 (TXD)P3.1 (T0)P3.4 (T1)P3.5 XTAL2 XTAL1 GND (INT0)P3.2 (INT1)P3.3 (RD)P3.7 (WR)P3.6 Vcc P0.0(AD0 ) P0.1(AD1) P0.2(AD2 ) P0.3(AD3) P0.4(AD4) P0.5(AD5) P0.6(AD6) P0.7(AD7) EA/VPP ALE/PROG PSEN P2.7(A15) P2.6(A14 ) P2.5(A13 ) P2.4(A12 ) P2.3(A11 ) P2.2(A10) P2.1(A9) P2.0(A8) 8051 (8031)

 Vcc （ pin 40 ）： Vcc provides supply voltage to the chip. The voltage source is +5V.  GND （ pin 20 ）： ground  XTAL1 and XTAL2 （ pins 19,18 ）

Figure (a). XTAL Connection to 8051 C2 30pF C1 30pF XTAL2 XTAL1 GND  Using a quartz crystal oscillator  We can observe the frequency on the XTAL2 pin.

 RST （ pin 9 ）： reset  It is an input pin and is active high （ normally low ） . The high pulse must be high at least 2 machine cycles.  It is a power-on reset. Upon applying a high pulse to RST, the microcontroller will reset and all values in registers will be lost. Reset values of some 8051 registers

30 pF 30 pF 8.2 K 10 uF + Vcc 11.0592 MHz EA/VPP X1 X2 RST 31 19 18 9

 /EA （ pin 31 ）： external access  There is no on-chip ROM in 8031 and 8032 .  The /EA pin is connected to GND to indicate the code is stored externally.  /PSEN ＆ ALE are used for external ROM.  For 8051, /EA pin is connected to Vcc.  “/” means active low.  /PSEN （ pin 29 ）： program store enable  This is an output pin and is connected to the OE pin of the ROM.

 ALE （ pin 30 ）： address latch enable  It is an output pin and is active high.  8051 port 0 provides both address and data.  The ALE pin is used for de-multiplexing the address and data by connecting to the G pin of the 74LS373 latch.  I/O port pins  The four ports P0, P1, P2, and P3.  Each port uses 8 pins.  All I/O pins are bi-directional. .

 The 8051 has four I/O ports  Port 0 （ pins 32-39 ）： P0 （ P0.0 ～ P0.7 ）  Port 1 （ pins 1-8 ）： P1 （ P1.0 ～ P1.7 ）  Port 2 （ pins 21-28 ）： P2 （ P2.0 ～ P2.7 ）  Port 3 （ pins 10-17 ）： P3 （ P3.0 ～ P3.7 ）  Each port has 8 pins. Named P0.X （ X=0,1,...,7 ） , P1.X, P2.X, P3.X Ex ： P0.0 is the bit 0 （ LSB ） of P0 Ex ： P0.7 is the bit 7 （ MSB ） of P0 These 8 bits form a byte.  Each port can be used as input or output (bi-direction). 

 Each pin of I/O ports  Internal CPU bus ： communicate with CPU  A D latch store the value of this pin  D latch is controlled by “Write to latch”  Write to latch ＝ 1 ： write data into the D latch  2 Tri-state buffer ：  TB1: controlled by “Read pin”  Read pin ＝ 1 ： really read the data present at the pin  TB2: controlled by “Read latch”  Read latch ＝ 1 ： read value from internal latch  A transistor M1 gate  Gate=0: open  Gate=1: close

8051 IC D Q Clk Q Vcc Load(L1) Read latch Read pin Write to latch Internal CPU bus M1 P1.X pin P1.X TB1 TB2 

D Q Clk Q Vcc Load(L1) Read latch Read pin Write to latch Internal CPU bus M1 P1.X pin P1.X 8051 IC 2. output pin is Vcc 1. write a 1 to the pin 1 0 output 1 TB1 TB2

D Q Clk Q Vcc Load(L1) Read latch Read pin Write to latch Internal CPU bus M1 P1.X pin P1.X 8051 IC 2. output pin is ground 1. write a 0 to the pin 0 1 output 0 TB1 TB2

8051 IC D Q Clk Q Read latch Read pin Write to latch Internal CPU bus M1 P0.X pin P1.X TB1 TB2 P1.x

P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 DS5000 8751 8951 Vcc 10 K Port 0

Port 1 can be used as input or output  In contrast to port 0, this port does not need any pull-up resistors since it already has pull-up resistors internally  Upon reset, port 1 is configured as an input port  To make port 1 an input port, it must be programmed as such by writing 1 to all its bits

 Port 2 can be used as input or output  Just like P1, port 2 does not need any pull-up resistors since it already has pull-up resistors internally  Upon reset, port 2 is configured as an input port  To make port 2 an input port, it must be programmed as such by writing 1 to all its bits  In many 8051-based system, P2 is used as simple I/O  In 8031-based systems, port 2 must be used along with P0 to provide the 16-bit address for the external memory

Port 3 can be used as input or output  Port 3 does not need any pull-up resistors  Port 3 is configured as an input port upon reset, this is not the way it is most commonly used  Port 3 has the additional function of providing some extremely important signals

The CPU can access data in various ways, which are called addressing modes

 The register addressing instruction involves information transfer between registers  Example: MOV R0, A  The instruction transfers the accumulator content into the R0 register. The register bank (Bank 0, 1, 2 or 3) must be specified prior to this instruction.

 This mode allows you to specify the operand by giving its actual memory address (typically specified in hexadecimal format) or by giving its abbreviated name (e.g. P3) Note: Abbreviated SFR names are defined in the “C8051F020.inc” header file  Example: MOV A, P3 ;Transfer the contents of ;Port 3 to the accumulator MOV A, 020H ;Transfer the contents of RAM ;location 20H to the accumulator

 This mode uses a pointer to hold the effective address of the operand  Only registers R0, R1 and DPTR can be used as the pointer registers  The R0 and R1 registers can hold an 8-bit address, whereas DPTR can hold a 16-bit address  Examples: MOV @R0,A ;Store the content of ;accumulator into the memory ;location pointed to by ;register R0. R0 could have an ;8-bit address, such as 60H. MOVX A,@DPTR ;Transfer the contents from ;the memory location ;pointed to by DPTR into the ;accumulator. DPTR could have a ;16-bit address, such as 1234H.

 This mode of addressing uses either an 8- or 16-bit constant value as the source operand  This constant is specified in the instruction, rather than in a register or a memory location  The destination register should hold the same data size which is specified by the source operand  Examples: ADD A,#030H ;Add 8-bit value of 30H to ;the accumulator register ;(which is an 8-bit register). MOV DPTR,#0FE00H ;Move 16-bit data constant ;FE00H into the 16-bit Data ;Pointer Register.

 This mode of addressing is used with some type of jump instructions, like SJMP (short jump) and conditional jumps like JNZ  These instructions transfer control from one part of a program to another  The destination address must be within -128 and +127 bytes from the current instruction address because an 8- bit offset is used (28 = 256)  Example: GoBack: DEC A ;Decrement A JNZ GoBack ;If A is not zero, loop back

 Two instructions associated with this mode of addressing are ACALL and AJMP instructions  These are 2-byte instructions where the 11-bit absolute address is specified as the operand  The upper 5 bits of the 16-bit PC address are not modified. The lower 11 bits are loaded from this instruction. So, the branch address must be within the current 2K byte page of program memory (211 = 2048)  Example: ACALL PORT_INIT ;PORT_INIT should be ;located within 2k bytes. PORT_INIT: MOV P0, #0FH ;PORT_INIT subroutine

 This mode of addressing is used with the LCALL and LJMP instructions  It is a 3-byte instruction and the last 2 bytes specify a 16- bit destination location where the program branches  It allows use of the full 64 K code space  The program will always branch to the same location no matter where the program was previously  Example: LCALL TIMER_INIT ;TIMER_INIT address (16-bits ;long) is specified as the ;operand; In C, this will be a ;function call: Timer_Init(). TIMER_INIT: ORL TMOD,#01H ;TIMER_INIT subroutine

 The Indexed addressing is useful when there is a need to retrieve data from a look-up table  A 16-bit register (data pointer) holds the base address and the accumulator holds an 8-bit displacement or index value  The sum of these two registers forms the effective address for a JMP or MOVC instruction  Example: MOV A,#08H ;Offset from table start MOV DPTR,#01F00H ;Table start address MOVC A,@A+DPTR ;Gets target value from the table ;start address + offset and puts it ;in A.  After the execution of the above instructions, the program will branch to address 1F08H (1F00H+08H) and transfer into the accumulator the data byte retrieved from that location (from the look-up table)

 The C8051F020 instructions are divided into five functional groups:  Arithmetic operations  Logical operations  Data transfer operations  Boolean variable operations  Program branching operations

 With arithmetic instructions, the C8051F020 CPU has no special knowledge of the data format (e.g. signed binary, unsigned binary, binary coded decimal, ASCII, etc.)  The appropriate status bits in the PSW are set when specific conditions are met, which allows the user software to manage the different data formats  [@Ri] implies contents of memory location pointed to by R0 or R1  Rn refers to registers R0-R7 of the currently selected register bank

 ADD adds the data byte specified by the source operand to the accumulator, leaving the result in the accumulator  ADDC adds the data byte specified by the source operand, the carry flag and the accumulator contents, leaving the result in the accumulator  Operation of both the instructions, ADD and ADDC, can affect the carry flag (CY), auxiliary carry flag (AC) and the overflow flag (OV)  CY=1 If there is a carryout from bit 7; cleared otherwise  AC =1 If there is a carryout from the lower 4-bit of A i.e. from bit 3; cleared otherwise  OV=1 If the signed result cannot be expressed within the number of bits in the destination operand; cleared otherwise

 SUBB subtracts the specified data byte and the carry flag together from the accumulator, leaving the result in the accumulator CY=1 If a borrow is needed for bit 7; cleared otherwise AC =1 If a borrow is needed for bit 3, cleared otherwise OV=1 If a borrow is needed into bit 6, but not into bit 7, or into bit 7, but not into bit 6.  Example: The accumulator holds 0C1H (11000001B), Register1 holds 40H (01000000B) and the CY=1.The instruction, SUBB A, R1 gives the value 70H (01110000B) in the accumulator, with the CY=0 and AC=0 but OV=1

 Increments the data variable by 1. The instruction is used in register, direct or register direct addressing modes  Example: INC 6FH If the internal RAM location 6FH contains 30H, then the instruction increments this value, leaving 31H in location 6FH  Example: MOV R1, #5E INC R1 INC @R1  If R1=5E (01011110) and internal RAM location 5FH contains 20H, the instructions will result in R1=5FH and internal RAM location 5FH to increment by one to 21H

 The data variable is decremented by 1  The instruction is used in accumulator, register, direct or register direct addressing modes  A data of value 00H underflows to FFH after the operation  No flags are affected

 Increments the 16-bit data pointer by 1  DPTR is the only 16-bit register that can be incremented  The instruction adds one to the contents of DPTR directly

 Multiplies A & B and the 16-bit result stored in [B15-8], [A7-0]  Multiplies the unsigned 8-bit integers in the accumulator and the B register  The Low order byte of the 16-bit product will go to the accumulator and the High order byte will go to the B register  If the product is greater than 255 (FFH), the overflow flag is set; otherwise it is cleared. The carry flag is always cleared.  If ACC=85 (55H) and B=23 (17H), the instruction gives the product 1955 (07A3H), so B is now 07H and the accumulator is A3H. The overflow flag is set and the carry flag is cleared.

 Divides A by B  The integer part of the quotient is stored in A and the remainder goes to the B register  If ACC=90 (5AH) and B=05(05H), the instruction leaves 18 (12H) in ACC and the value 00 (00H) in B, since 90/5 = 18 (quotient) and 00 (remainder)  Carry and OV are both cleared  If B contains 00H before the division operation, then the values stored in ACC and B are undefined and an overflow flag is set. The carry flag is cleared.

 This is a decimal adjust instruction  It adjusts the 8-bit value in ACC resulting from operations like ADD or ADDC and produces two 4-bit digits (in packed Binary Coded Decimal (BCD) format)  Effectively, this instruction performs the decimal conversion by adding 00H, 06H, 60H or 66H to the accumulator, depending on the initial value of ACC and PSW  If ACC bits A3-0 are greater than 9 (xxxx1010-xxxx1111), or if AC=1, then a value 6 is added to the accumulator to produce a correct BCD digit in the lower order nibble  If CY=1, because the high order bits A7-4 is now exceeding 9 (1010xxxx-1111xxxx), then these high order bits will be increased by 6 to produce a correct proper BCD in the high order nibble but not clear the carry

 Logical instructions perform Boolean operations (AND, OR, XOR, and NOT) on data bytes on a bit-by-bit basis  Examples: ANL A, #02H ;Mask bit 1 ORL TCON, A ;TCON=TCON-OR- A

 This instruction performs the logical AND operation on the source and destination operands and stores the result in the destination variable  No flags are affected  Example: ANL A,R2 If ACC=D3H (11010011) and R2=75H (01110101), the result of the instruction is ACC=51H (01010001)  The following instruction is also useful when there is a need to mask a byte  Example: ANL P1,#10111001B

 This instruction performs the logical OR operation on the source and destination operands and stores the result in the destination variable  No flags are affected  Example: ORL A,R2 If ACC=D3H (11010011) and R2=75H (01110101), the result of the instruction is ACC=F7H (11110111)  Example: ORL P1,#11000010B This instruction sets bits 7, 6, and 1 of output Port 1

 This instruction performs the logical XOR (Exclusive OR) operation on the source and destination operands and stores the result in the destination variable  No flags are affected  Example: XRL A,R0 If ACC=C3H (11000011) and R0=AAH (10101010), then the instruction results in ACC=69H (01101001)  Example: XRL P1,#00110001 This instruction complements bits 5, 4, and 0 of output Port 1

CLR A  This instruction clears the accumulator (all bits set to 0)  No flags are affected  If ACC=C3H, then the instruction results in ACC=00H CPL A  This instruction logically complements each bit of the accumulator (one’s complement)  No flags are affected  If ACC=C3H (11000011), then the instruction results in ACC=3CH (00111100)

 The 8 bits in the accumulator are rotated one bit to the left. Bit 7 is rotated into the bit 0 position.  No flags are affected  If ACC=C3H (11000011), then the instruction results in ACC=87H (10000111) with the carry unaffected

 The instruction rotates the accumulator contents one bit to the left through the carry flag  Bit 7 of the accumulator will move into carry flag and the original value of the carry flag will move into the Bit 0 position  No other flags are affected  If ACC=C3H (11000011), and the carry flag is 1, the instruction results in ACC=87H (10000111) with the carry flag set

 The 8 bits in the accumulator are rotated one bit to the right. Bit 0 is rotated into the bit 7 position.  No flags are affected  If ACC=C3H (11000011), then the instruction results in ACC=E1H (11100001) with the carry unaffected

 The instruction rotates the accumulator contents one bit to the right through the carry flag  The original value of carry flag will move into Bit 7 of the accumulator and Bit 0 rotated into carry flag  No other flags are affected  If ACC=C3H (11000011), and the carry flag is 0, the instruction results in ACC=61H (01100001) with the carry flag set

 This instruction interchanges the low order 4-bit nibbles (A3-0) with the high order 4-bit nibbles (A7-4) of the ACC  The operation can also be thought of as a 4-bit rotate instruction  No flags are affected  If ACC=C3H (11000011), then the instruction leaves ACC=3CH (00111100)

 Data transfer instructions can be used to transfer data between an internal RAM location and an SFR location without going through the accumulator  It is also possible to transfer data between the internal and external RAM by using indirect addressing  The upper 128 bytes of data RAM are accessed only by indirect addressing and the SFRs are accessed only by direct addressing Mnemonic Description MOV @Ri, direct [@Ri] = [direct] MOV @Ri, #data [@Ri] = immediate data MOV DPTR, #data 16 [DPTR] = immediate data MOVC A,@A+DPTR A = Code byte from [@A+DPTR] MOVC A,@A+PC A = Code byte from [@A+PC] MOVX A,@Ri A = Data byte from external ram [@Ri] MOVX A,@DPTR A = Data byte from external ram [@DPTR] MOVX @Ri, A External[@Ri] = A MOVX @DPTR,A External[@DPTR] = A PUSH direct Push into stack POP direct Pop from stack XCH A,Rn A = [Rn], [Rn] = A XCH A, direct A = [direct], [direct] = A XCH A, @Ri A = [@Rn], [@Rn] = A XCHD A,@Ri Exchange low order digits

 This instruction moves the source byte into the destination location  The source byte is not affected, neither are any other registers or flags  Example: MOV R1,#60 ;R1=60H MOV A,@R1 ;A=[60H] MOV R2,#61 ;R2=61H ADD A,@R2 ;A=A+[61H] MOV R7,A ;R7=A  If internal RAM locations 60H=10H, and 61H=20H, then after the operations of the above instructions R7=A=30H. The data contents of memory locations 60H and 61H remain intact.

 This instruction loads the data pointer with the 16-bit constant and no flags are affected  Example: MOV DPTR,#1032  This instruction loads the value 1032H into the data pointer, i.e. DPH=10H and DPL=32H.

 This instruction moves a code byte from program memory into ACC  The effective address of the byte fetched is formed by adding the original 8-bit accumulator contents and the contents of the base register, which is either the data pointer (DPTR) or program counter (PC)  16-bit addition is performed and no flags are affected  The instruction is useful in reading the look-up tables in the program memory  If the PC is used, it is incremented to the address of the following instruction before being added to the ACC  Example: CLR A LOC1: INC A MOVC A,@A + PC RET Look_up DB 10H DB 20H DB 30H DB 40H  The subroutine takes the value in the accumulator to 1 of 4 values defined by the DB (define byte) directive  After the operation of the subroutine it returns ACC=20H

 This instruction transfers data between ACC and a byte of external data memory  There are two forms of this instruction, the only difference between them is whether to use an 8-bit or 16-bit indirect addressing mode to access the external data RAM  The 8-bit form of the MOVX instruction uses the EMI0CN SFR to determine the upper 8 bits of the effective address to be accessed and the contents of R0 or R1 to determine the lower 8 bits of the effective address to be accessed  Example: MOV EMI0CN,#10H ;Load high byte of ;address into EMI0CN. MOV R0,#34H;Load low byte of ;address into R0(or R1). MOVX A,@R0 ;Load contents of 1034H ;into ACC.

 The 16-bit form of the MOVX instruction accesses the memory location pointed to by the contents of the DPTR register  Example: MOV DPTR,#1034H ;Load DPTR with 16 bit ;address to read (1034H). MOVX A,@DPTR ;Load contents of 1034H ;into ACC.  The above example uses the 16-bit immediate MOV DPTR instruction to set the contents of DPTR  Alternately, the DPTR can be accessed through the SFR registers DPH, which contains the upper 8 bits of DPTR, and DPL, which contains the lower 8 bits of DPTR

 This instruction increments the stack pointer (SP) by 1  The contents of Direct, which is an internal memory location or a SFR, are copied into the internal RAM location addressed by the stack pointer  No flags are affected  Example: PUSH 22H PUSH 23H  Initially the SP points to memory location 4FH and the contents of memory locations 22H and 23H are 11H and 12H respectively. After the above instructions, SP=51H, and the internal RAM locations 50H and 51H will store 11H and 12H respectively.

 This instruction reads the contents of the internal RAM location addressed by the stack pointer (SP) and decrements the stack pointer by 1. The data read is then transferred to the Direct address which is an internal memory or a SFR. No flags are affected.  Example: POP DPH POP DPL  If SP=51H originally and internal RAM locations 4FH, 50H and 51H contain the values 30H, 11H and 12H respectively, the instructions above leave SP=4FH and DPTR=1211H POP SP  If the above line of instruction follows, then SP=30H. In this case, SP is decremented to 4EH before being loaded with the value popped (30H)

 This instruction swaps the contents of ACC with the contents of the indicated data byte  Example: XCH A,@R0  Suppose R0=2EH, ACC=F3H (11110011) and internal RAM location 2EH=76H (01110110). The result of the above instruction leaves RAM location 2EH=F3H and ACC=76H.

 This instruction exchanges the low order nibble of ACC (bits 0-3), with that of the internal RAM location pointed to by Ri register  The high order nibbles (bits 7-4) of both the registers remain the same  No flags are affected  Example: XCHD A,@R0 If R0=2EH, ACC=76H (01110110) and internal RAM location 2EH=F3H (11110011), the result of the instruction leaves RAM location 2EH=F6H (11110110) and ACC=73H (01110011)

 The C8051F020 processor can perform single bit operations  The operations include set, clear, and, or and complement instructions  Also included are bit–level moves or conditional jump instructions  All bit accesses use direct addressing  Examples: SETB TR0 ;Start Timer0. POLL: JNB TR0, POLL ;Wait till timer overflows. Mnemonic Description CLR C Clear C CLR bit Clear direct bit SETB C Set C SETB bit Set direct bit CPL C Complement c CPL bit Complement direct bit ANL C,bit AND bit with C ANL C,/bit AND NOT bit with C ORL C,bit OR bit with C ORL C,/bit OR NOT bit with C MOV C,bit MOV bit to C MOV bit,C MOV C to bit JC rel Jump if C set JNC rel Jump if C not set JB bit,rel Jump if specified bit set JNB bit,rel Jump if specified bit not set JBC bit,rel if specified bit set then clear it and jump

 This operation clears (reset to 0) the specified bit indicated in the instruction  No other flags are affected  CLR instruction can operate on the carry flag or any directly- addressable bit  Example: CLR P2.7 If Port 2 has been previously written with DCH (11011100), then the operation leaves the port set to 5CH (01011100)

 This operation sets the specified bit to 1  SETB instruction can operate on the carry flag or any directly- addressable bit  No other flags are affected  Example: SETB C SETB P2.0  If the carry flag is cleared and the output Port 2 has the value of 24H (00100100), then the result of the instructions sets the carry flag to 1 and changes the Port 2 value to 25H (00100101)

 This operation complements the bit indicated by the operand  No other flags are affected  CPL instruction can operate on the carry flag or any directly- addressable bit  Example: CPL P2.1 CPL P2.2  If Port 2 has the value of 53H (01010011) before the start of the instructions, then after the execution of the instructions it leaves the port set to 55H (01010101)

 This instruction ANDs the bit addressed with the Carry bit and stores the result in the Carry bit itself  If the source bit is a logical 0, then the instruction clears the carry flag; else the carry flag is left in its original value  If a slash (/) is used in the source operand bit, it means that the logical complement of the addressed source bit is used, but the source bit itself is not affected  No other flags are affected  Example: MOV C,P2.0 ;Load C with input pin ;state of P2.0. ANL C,P2.7 ;AND carry flag with ;bit 7 of P2. MOV P2.1,C ;Move C to bit 1 of Port 2. ANL C,/OV ;AND with inverse of OV flag.  If P2.0=1, P2.7=0 and OV=0 initially, then after the above instructions, P2.1=0, CY=0 and the OV remains unchanged, i.e. OV=0

 This instruction ORs the bit addressed with the Carry bit and stores the result in the Carry bit itself  It sets the carry flag if the source bit is a logical 1; else the carry is left in its original value  If a slash (/) is used in the source operand bit, it means that the logical complement of the addressed source bit is used, but the source bit itself is not affected  No other flags are affected  Example: MOV C,P2.0 ;Load C with input pin ;state of P2.0. ORL C,P2.7 ;OR carry flag with ;bit 7 of P2. MOV P2.1,C ;Move C to bit 1 of ;port 2. ORL C,/OV ;OR with inverse of OV ;flag.

 The instruction loads the value of source operand bit into the destination operand bit  One of the operands must be the carry flag; the other may be any directly- addressable bit  No other register or flag is affected  Example: MOV P2.3,C MOV C,P3.3 MOV P2.0,C  If P2=C5H (11000101), P3.3=0 and CY=1 initially, then after the above instructions, P2=CCH (11001100) and CY=0.

 This instruction branches to the address, indicated by the label, if the carry flag is set, otherwise the program continues to the next instruction  No flags are affected  Example: CLR C SUBB A,R0 JC ARRAY1 MOV A,#20H  The carry flag is cleared initially. After the SUBB instruction, if the value of A is smaller than R0, then the instruction sets the carry flag and causes program execution to branch to ARRAY1 address, otherwise it continues to the MOV instruction.

 This instruction branches to the address, indicated by the label, if the carry flag is not set, otherwise the program continues to the next instruction  No flags are affected. The carry flag is not modified.  Example: CLR C SUBB A,R0 JNC ARRAY2 MOV A,#20H  The above sequence of instructions will cause the jump to be taken if the value of A is greater than or equal to R0. Otherwise the program will continue to the MOV instruction.

 This instruction jumps to the address indicated if the destination bit is 1, otherwise the program continues to the next instruction  No flags are affected. The bit tested is not modified.  Example: JB ACC.7,ARRAY1 JB P1.2,ARRAY2  If the accumulator value is 01001010 and Port 1=57H (01010111), then the above instruction sequence will cause the program to branch to the instruction at ARRAY2

 This instruction jumps to the address indicated if the destination bit is 0, otherwise the program continues to the next instruction  No flags are affected. The bit tested is not modified.  Example: JNB ACC.6,ARRAY1 JNB P1.3,ARRAY2  If the accumulator value is 01001010 and Port 1=57H (01010111), then the above instruction sequence will cause the program to branch to the instruction at ARRAY2

 If the source bit is 1, this instruction clears it and branches to the address indicated; else it proceeds with the next instruction  The bit is not cleared if it is already a 0. No flags are affected.  Example: JBC P1.3,ARRAY1 JBC P1.2,ARRAY2  If P1=56H (01010110), the above instruction sequence will cause the program to branch to the instruction at ARRAY2, modifying P1 to 52H (01010010)

 Program branching instructions are used to control the flow of program execution  Some instructions provide decision making capabilities before transferring control to other parts of the program (conditional branches). Mnemonic Description ACALL addr11 Absolute subroutine call LCALL addr16 Long subroutine call RET Return from subroutine RETI Return from interrupt AJMP addr11 Absolute jump LJMP addr16 Long jump SJMP rel Short jump JMP @A+DPTR Jump indirect JZ rel Jump if A=0 JNZ rel Jump if A NOT=0 CJNE A,direct,rel Compare and Jump if Not Equal CJNE A,#data,rel CJNE Rn,#data,rel CJNE @Ri,#data,rel DJNZ Rn,rel Decrement and Jump if Not Zero DJNZ direct,rel NOP No Operation

 This instruction unconditionally calls a subroutine indicated by the address  The operation will cause the PC to increase by 2, then it pushes the 16-bit PC value onto the stack (low order byte first) and increments the stack pointer twice  The PC is now loaded with the value addr11 and the program execution continues from this new location  The subroutine called must therefore start within the same 2 kB block of the program memory  No flags are affected  Example: ACALL LOC_SUB  If SP=07H initially and the label “LOC_SUB” is at program memory location 0567H, then executing the instruction at location 0230H, SP=09H, internal RAM locations 08H and 09H will contain 32H and 02H respectively and PC=0567H

 This instruction calls a subroutine located at the indicated address  The operation will cause the PC to increase by 3, then it pushes the 16-bit PC value onto the stack (low order byte first) and increments the stack pointer twice  The PC is then loaded with the value addr16 and the program execution continues from this new location  Since it is a Long call, the subroutine may therefore begin anywhere in the full 64 kB program memory address space  No flags are affected  Example: LCALL LOC_SUB  Initially, SP=07H and the label “LOC_SUB” is at program memory location 2034H. Executing the instruction at location 0230H, SP=09H, internal RAM locations 08H and 09H contain 33H and 02H respectively and PC=2034H

 This instruction returns the program from a subroutine  RET pops the high byte and low byte address of PC from the stack and decrements the SP by 2  The execution of the instruction will result in the program to resume from the location just after the “call” instruction  No flags are affected  Suppose SP=0BH originally and internal RAM locations 0AH and 0BH contain the values 30H and 02H respectively. The instruction leaves SP=09H and program execution will continue at location 0230H

 This instruction returns the program from an interrupt subroutine  RETI pops the high byte and low byte address of PC from the stack and restores the interrupt logic to accept additional interrupts  SP decrements by 2 and no other registers are affected. However the PSW is not automatically restored to its pre- interrupt status  After the RETI, program execution will resume immediately after the point at which the interrupt is detected  Suppose SP=0BH originally and an interrupt is detected during the instruction ending at location 0213H  Internal RAM locations 0AH and 0BH contain the values 14H and 02H respectively  The RETI instruction leaves SP=09H and returns program execution to location 0234H

 The AJMP instruction transfers program execution to the destination address which is located at the absolute short range distance (short range means 11-bit address)  The destination must therefore be within the same 2kB block of program memory  Example: AJMP NEAR  If the label NEAR is at program memory location 0120H, the AJMP instruction at location 0234H loads the PC with 0120H

 The LJMP instruction transfers program execution to the destination address which is located at the absolute long range distance (long range means 16-bit address)  The destination may therefore be anywhere in the full 64 kB program memory address space  No flags are affected  Example: LJMP FAR_ADR  If the label FAR_ADR is at program memory location 3456H, the LJMP instruction at location 0120H loads the PC with 3456H

 This is a short jump instruction, which increments the PC by 2 and then adds the relative value ‘rel’ (signed 8-bit) to the PC  This will be the new address where the program would branch to unconditionally  Therefore, the range of destination allowed is from -128 to +127 bytes from the instruction  Example: SJMP RELSRT  If the label RELSRT is at program memory location 0120H and the SJMP instruction is located at address 0100H, after executing the instruction, PC=0120H.

 This instruction adds the 8-bit unsigned value of the ACC to the 16-bit data pointer and the resulting sum is returned to the PC  Neither ACC nor DPTR is altered  No flags are affected  Example: MOV DPTR, #LOOK_TBL JMP @A + DPTR LOOK_TBL: AJMP LOC0 AJMP LOC1 AJMP LOC2 If the ACC=02H, execution jumps to LOC1  AJMP is a two byte instruction

 This instruction branches to the destination address if ACC=0; else the program continues to the next instruction  The ACC is not modified and no flags are affected  Example: SUBB A,#20H JZ LABEL1 DEC A  If ACC originally holds 20H and CY=0, then the SUBB instruction changes ACC to 00H and causes the program execution to continue at the instruction identified by LABEL1; otherwise the program continues to the DEC instruction

 This instruction branches to the destination address if any bit of ACC is a 1; else the program continues to the next instruction  The ACC is not modified and no flags are affected  Example: DEC A JNZ LABEL2 MOV RO, A  If ACC originally holds 00H, then the instructions change ACC to FFH and cause the program execution to continue at the instruction identified by LABEL2; otherwise the program continues to MOV instruction

 This instruction compares the magnitude of the dest-byte and the source-byte and branches if their values are not equal  The carry flag is set if the unsigned dest-byte is less than the unsigned integer source-byte; otherwise, the carry flag is cleared  Neither operand is affected  Example: CJNE R3,#50H,NEQU … … ;R3 = 50H NEQU: JC LOC1 ;If R3 < 50H … … ;R7 > 50H LOC1: … … ;R3 < 50H

 This instruction is ”decrement jump not zero”  It decrements the contents of the destination location and if the resulting value is not 0, branches to the address indicated by the source operand  An original value of 00H underflows to FFH  No flags are affected  Example: DJNZ 20H,LOC1 DJNZ 30H,LOC2 DJNZ 40H,LOC3  If internal RAM locations 20H, 30H and 40H contain the values 01H, 5FH and 16H respectively, the above instruction sequence will cause a jump to the instruction at LOC2, with the values 00H, 5EH, and 15H in the 3 RAM locations.  Note, the first instruction will not branch to LOC1 because the [20H] = 00H, hence the program continues to the second instruction  Only after the execution of the second instruction (where the location [30H] = 5FH), then the branching takes place

 This is the no operation instruction  The instruction takes one machine cycle operation time  Hence it is useful to time the ON/OFF bit of an output port  Example: CLR P1.2 NOP NOP NOP NOP SETB P1.2  The above sequence of instructions outputs a low-going output pulse on bit 2 of Port 1 lasting exactly 5 cycles.  Note a simple SETB/CLR generates a 1 cycle pulse, so four additional cycles must be inserted in order to have a 5-clock pulse width

106  Basic registers of the timer  Timer 0 and Timer 1 are 16 bits wide  each 16-bit timer is accessed as two separate registers of low byte and high byte.

107  Timer 0 registers  low byte register is called TL0 (Timer 0 low byte) and the high byte register is referred to as TH0 (Timer 0 high byte)  can be accessed like any other register, such as A, B, R0, R1, R2, etc.  "MOV TL0, #4 FH" moves the value 4FH into TL0  "MOV R5, TH0" saves TH0 (high byte of Timer 0) in R5

108 Figure 9–1 Timer 0 Registers

109  Timer 1 registers  also 16 bits  split into two bytes TL1 (Timer 1 low byte) and TH1 (Timer 1 high byte)  accessible in the same way as the registers of Timer 0.

110 Figure 9–2 Timer 1 Registers

111  TMOD (timer mode) register  timers 0 and 1 use TMOD register to set operation modes (only learn Mode 1 and 2)  8-bit register  lower 4 bits are for Timer 0  upper 4 bits are for Timer 1  lower 2 bits are used to set the timer mode  (only learn Mode 1 and 2)  upper 2 bits to specify the operation  (only learn timer operation)

112 Figure 9–3 TMOD Register

113  Clock source for timer  timer needs a clock pulse to tick  if C/T = 0, the crystal frequency attached to the 8051 is the source of the clock for the timer  frequency for the timer is always 1/12th the frequency of the crystal attached to the 8051  XTAL = 11.0592 MHz allows the 8051 system to communicate with the PC with no errors  In our case, the timer frequency is 1MHz since our crystal frequency is 12MHz

114  Mode 0 Programming  works like mode 1  13-bit timer instead of 16 bit  13-bit counter hold values 0000 to 1FFFH  when the timer reaches its maximum of 1FFFH, it rolls over to 0000, and TF is set

115  Mode 1 programming  16-bit timer, values of 0000 to FFFFH  TH and TL are loaded with a 16-bit initial value  timer started by "SETB TR0" for Timer 0 and "SETB TR1" for Timer l  timer count ups until it reaches its limit of FFFFH  rolls over from FFFFH to 0000H  sets TF (timer flag)  when this timer flag is raised, can stop the timer with "CLR TR0" or "CLR TR1“  after the timer reaches its limit and rolls over, the registers TH and TL must be reloaded with the original value and TF must be reset to 0

116 Figure 9–5a Timer 0 with External Input (Mode 1)

117 Figure 9–5b Timer 1 with External Input (Mode 1)

118 Steps to program in mode 1  Set timer mode 1 or 2  Set TL0 and TH0 (for mode 1 16 bit mode)  Set TH0 only (for mode 2 8 bit auto reload mode)  Run the timer  Monitor the timer flag bit

120  Finding values to be loaded into the timer  XTAL = 11.0592 MHz (12MHz)  divide the desired time delay by 1.085s (1s) to get n  65536 – n = N  convert N to hex yyxx  set TL = xx and TH = yy

121  T = 1/50 Hz = 20 ms  1/2 of it for the high and low portions of the pulse = 10 ms  10 ms / 1.085 us = 9216  65536 - 9216 = 56320 in decimal = DC00H  TL = 00 and TH = DCH  The calculation for 12MHz crystal uses the same steps

123  Generating a large time delay  size of the time delay depends  crystal frequency  timer's 16-bit register in mode 1  largest time delay is achieved by making both TH and TL zero  what if that is not enough?

124  Using Windows calculator to find TH, TL  Windows scientific calculator can be use to find the TH, TL values  Lets say we would like to find the TH, TL values for a time delay that uses 35,000 clocks of 1.085s 1. open scientific calculator and select decimal 2. enter 35,000 3. select hex - converts 35,000 to hex 88B8H 4. select +/- to give -35000 decimal (7748H) 5. the lowest two digits (48) of this hex value are for TL and the next two (77) are for TH

126  Mode 2 programming  8-bit timer, allows values of 00 to FFH  TH is loaded with the 8-bit value  a copy is given to TL  timer is started by ,"SETB TR0" or "SETB TR1“  starts to count up by incrementing the TL register  counts up until it reaches its limit of FFH  when it rolls over from FFH to 00, it sets high TF  TL is reloaded automatically with the value in TH  To repeat, clear TF  mode 2 is an auto-reload mode

127  Steps to program in mode 2 1. load TMOD, select mode 2 2. load the TH 3. start timer 4. monitor the timer flag (TF) with "JNB” 5. get out of the loop when TF=1 6. clear TF 7. go back to Step 4 since mode 2 is auto-reload

129  C/T bit in TMOD register  used as a timer, the 8051's crystal is used as the source of the fre quency  used as a counter, pulse outside the 8051 increments the TH, TL registers  counter mode, TMOD and TH, TL registers are the same as for the timer  timer modes are the same as well

130  C/T bit in TMOD register  C/T bit in the TMOD register decides the source of the clock for the timer  C/T = 0, timer gets pulses from crystal  C/T = 1, the timer used as counter and gets pulses from outside the 8051  C/T = 1, the counter counts up as pulses are fed from pins 14 and 15  pins are called T0 (Timer 0 input) and T1 (Timer 1 input)  these two pins belong to port 3  Timer 0, when C/T = 1, pin P3.4 provides the clock pulse and the counter counts up for each clock pulse coming from that pin  Timer 1, when C/T = 1 each clock pulse coming in from pin P3.5 makes the counter count up

131 Table 9–1 Port 3 Pins Used For Timers 0 and 1

132 P2 is connected to 8 LEDs and input T1 to pulse. to LEDs

133 Figure 9–6 Timer 0 with External Input (Mode 2)

134 Figure 9–7 Timer 1 with External Input (Mode 2)

137 Table 9–1 Port 3 Pins Used For Timers 0 and 1

138  TCON register  TR0 and TR1 flags turn on or off the timers  bits are part of a register called TCON (timer control)  upper four bits are used to store the TF and TR bits of both Timer 0 and Timer 1  lower four bits are set aside for controlling the interrupt bits  "SETB TRl" and "CLR TRl“  "SETB TCON. 6" and "CLR TCON. 6“

139 Table 9–2 Equivalent Instructions for the Timer Control Register (TCON)

140  The case of GATE = 1 in TMOD  GATE = 0, the timer is started with instructions "SETB TR0" and "SETB TR1“  GATE = 1, the start and stop of the timers are done externally through pins P3.2 and P3.3  allows us to start or stop the timer externally at any time via a simple switch

141 Figure 9–8 Timer/Counter 0

142 Figure 9–9 Timer/Counter 1

Port 0 (enable Ex. Memory) Port 2 ALE Address Latch Enable EA’ PSEN’ RD’ WR’ Ex.Data RAM write OE’ A8 - A15 A0 – A7 D0 – D7 Ex. Data RAM Reade Extensl Code Memory ROM or EPROM 8051 adress multiplex latch

INTERFACING ADC804 TO 8051 ADC808/809 Chip with 8 analog channel. This means this kind of chip allows to monitor 8 different transducers. • ADC804 has only ONE analog input: Vin(+). • ALE: Latch in the address • Start : Start of conversion (same as WR in 804) • OE: output enable (same as RD in 804) • EOC: End of Conversion (same as INTR in 804)

Make CS=0 and send a low-to-high to pin WR to start the conversion. • Keep monitoring INTR -If INTR =0, the conversion is finished and we can go to the next step. – If INTR=1, keep polling until it goes low. • After INTR=0, we make CS=0 and send a high-to-low pulse to RD to get the data out of the ADC804 chip.

Parallel: expensive - short distance – fast – no modulation Serial :cheaper– long (two different cities by modem)-slow

Basics of serial communication

In asynchronous transmission When there is no transfer the signal is high Transmission begins with a start (low) bit LSB first Finally 1 stop bit (high) Data transfer rate (baud rate) is stated in bps

 Create in 1960 and updated in 1969  Logic 1 : -3 to -25 volt  Logic 0 : 3 to 25 volt  To Connect TXD to RXD and RXD to TXD from pc to 8051 you must use max232 to convert signal from TTL level to RS232 level  The baud rate of the 8051 must matched the baud rate of the pc  PC standard baud rate (see hyper terminal configuration)  2400-4800-9600-14400-19200-28800-33600- 57600 1 DCD 2 RD 3 TD 4 DTR 5 GND 6 DSR 7 RTS 8 CTS 9 RI

SBUF register MOV SBUF,#’D’ ;load SBUF=44H, ASCII for ‘D’ MOV SBUF,A ;copy accumulator into SBUF MOV A,SBUF ;copy SBUF into accumulator

SM2 : used for multi processor communication REN : receive enable (by software enable/disable) TB8 : transmit bit8 RB8 : receive bit 8 TI : transmit interrupt flag set by HW after send , clear by SW RI : receive interrupt flag set by HW after received ,clear by SW SM0 RI TI RB8 TB8 REN SM2 SM1 7 6 5 4 3 2 1 0 SM0 SM1 MODE operation transmit rate 0 0 0 shift register fixed (xtal/12) 0 1 1 8 bit UART variable (timer1) 1 0 2 9 bit UART fixed (xtal/32 or xtal/64) 1 1 3 9 bit UART variable (timer1) SM0 : mode specifier SM1 : mode specifier

 Mode 0 :  Serial data enters and exits through RxD  TxD outputs the shift clock.  8 bits are transmitted/received(LSB first)  The baud rate is fixed a 1/12 the oscillator frequency.  Application  Port expansion 8051 TXD RXD Shift register clk data

One machine cycle oscillator cycle RXD (data) TXD (clock pulse) MOV SCON,#0001xxxxB Wait: JNB RI,WAIT CLR RI MOV A,SBUF MOV SCON,#0001xxxxB Wait: JNB TI,WAIT CLR TI MOV SBUF,A

 Mode 1  Ten bits are transmitted (through TxD) or received (through RxD) (A start bit (0), 8 data bits (LSB first), and a stop bit (1) )  On receive, the stop bit goes into RB8 in SCON  the baud rate is determined by the Timer 1 overflow rate.  Timer1 clock is 1/32 machine cycle (MC=1/12 XTAL) • Timer clock can be programmed as 1/16 of machine cycle • Transmission is initiated by any instruction that uses SBUF as a destination register.

MOV TMOD,#20H ;TIMER 1 MODE 2 MOV TH1,#-3 ;9600 BAUD MOV SCON,#50H ;REN enable SETB TR1 ;start timer1 AGAIN: MOV SBUF, # “A” WAIT: JNB TI,WAIT CLR TI SJMP AGAIN Serial example(1)

MOV TMOD,#20H ;TIMER 1 MODE 2 MOV TH1,#-3 ;9600 BAUD MOV SCON,#50H ;REN enable SETB TR1 ;start timer1 WAIT: JNB RI,WAIT MOV A,SBUF CLR RI SJMP WAIT Serial example(2)

An example of sending a message. ;initialization MOV TMOD,#20H MOV TH1,#-12 MOV SCON,#50H ;begin to trnasmit SETB TR1 AGAIN1: MOV A,#‘G' CALL TRANSS MOV A,#‘O' CALL TRANSS MOV A,#‘O' CALL TRANSS MOV A,#‘D' CALL TRANSS SJMP AGAIN1 ;seial transmiting subroutine TRANSS: MOV SBUF,A AGAIN2: JNB TI,AGAIN2 CLR TI RET END

 Mode 2 :  Eleven bits are transmitted (through TxD), received (through RxD)  A start bit (0)  8 data bits (LSB first)  A programmable 9th data bit  and a stop bit (1)  On transmit, the 9th bit (TB8) can be assigned 0 or 1.  On receive, the 9the data bit goes into RB8 in SCON.  the 9th can be parity bit  The baud rate is programmable to 1/32 or 1/64 the oscillator frequency in Mode 2 by SMOD bit in PCO register  Mode 3  Same as mode 2  But may have a variable baud rate generated from Timer 1.

 Bit 7 of PCON register  If SMOD=1 double baud rate  PCON is not bit addressable  How to set SMOD Mov a, pcon Setb acc.7 Mov pcon,a

 A standard for applications where power consumption is critical  two power reducing modes  Idle  Power down

 An instruction that sets PCON.0 causes Idle mode  Last instruction executed before going into the Idle mode  the internal CPU clock is gated off  Interrupt, Timer, and Serial Port functions act normally.  All of registers , ports and internal RAM maintain their data during Idle  ALE and PSEN hold at logic high levels  Any interrupt  will cause PCON.0 to be cleared by HW (terminate Idle mode)  then execute ISR  with RETI return and execute next instruction after Idle instruction.  RST signal clears the IDL bit directly

 An instruction that sets PCON.1 causes power dowm mode  Last instruction executed before going into the power down mode  the on-chip oscillator is stopped.  all functions are stopped,the contents of the on-chip RAM and Special Function Registers are maintained.  The ALE and PSEN output are held low  The reset that terminates Power Down

Org 0000h Ljmp main Org 0003h Orl pcon,#02h ;power down mode Reti Org 0030h Main: …… …… …… Orl pcon,#01h ;Idle mode end

 An interrupt is an external or internal event that interrupts the microcontroller to inform it that a device needs its service. Interrupts vs. Polling  A single microcontroller can serve several devices.  There are two ways to do that:  interrupts  polling.  The program which is associated with the interrupt is called the interrupt service routine (ISR) or interrupt handler.

Steps in executing an interrupt  Finish current instruction and saves the PC on stack.  Jumps to a fixed location in memory depend on type of interrupt  Starts to execute the interrupt service routine until RETI (return from interrupt)  Upon executing the RETI the microcontroller returns to the place where it was interrupted. Get pop PC from stack

 Original 8051 has 6 sources of interrupts  Reset  Timer 0 overflow  Timer 1 overflow  External Interrupt 0  External Interrupt 1  Serial Port events (buffer full, buffer empty, etc)  Enhanced version has 22 sources  More timers, programmable counter array, ADC, more external interrupts, another serial port (UART)

Each interrupt has a specific place in code memory where program execution (interrupt service routine) begins. External Interrupt 0: 0003h Timer 0 overflow: 000Bh External Interrupt 1: 0013h Timer 1 overflow: 001Bh Serial : 0023h Timer 2 overflow(8052+) 002bh Note: that there are only 8 memory locations between vectors.

Interrupt Enable (IE) register All interrupt are disabled after reset We can enable and disable them bye IE

Enabling and disabling an interrupt by bit operation Recommended in the middle of program SETB EA ;Enable All SETB ET0 ;Enable Timer0 ovrf SETB ET1 ;Enable Timer1 ovrf SETB EX0 ;Enable INT0 SETB EX1 ;Enable INT1 SETB ES ;Enable Serial port by mov instruction Recommended in the first of program MOV IE, #10010110B SETB IE.7 SETB IE.1 SETB IE.3 SETB IE.0 SETB IE.2 SETB IE.4

 Write a program using interrupts to simultaneously create 7 kHz and 500 Hz square waves on P1.7 and P1.6. 71s 143s 1ms 2ms P1.7 P1.6 8051

71s 143s 1ms 2ms P1.7 P1.6 8051 Solution ORG 0 LJMP MAIN ORG 000BH LJMP T0ISR ORG 001BH LJMP T1ISR ORG 0030H MAIN: MOV TMOD,#12H MOV TH0,#-71 SETB TR0 SETB TF1 MOV IE,#8AH MOV IE,#8AH SJMP $ T0ISR: CPL P1.7 RETI T1ISR: CLR TR1 MOV TH1,#HIGH(-1000) MOV TL1,#LOW(-1000) SETB TR1 CPL P1.6 RETI END

 Notice that  There is no need for a “CLR TFx” instruction in timer ISR  8051 clears the TF internally upon jumping to ISR  Notice that  We must reload timer in mode 1  There is no need on mode 2 (timer auto reload)

 By low nibble of Timer control register TCON  IE0 (IE1): External interrupt 0(1) edge flag.  set by CPU when external interrupt edge (H-to-L) is detected.  Does not affected by H-to-L while ISR is executed(no int on int)  Cleared by CPU when RETI executed.  does not latch low-level triggered interrupt  IT0 (IT1): interrupt 0 (1) type control bit.  Set/cleared by software  IT=1 edge trigger  IT=0 low-level trigger TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 Timer 1 Timer0 for Interrupt (MSB) (LSB)

External Interrupts IE0 (TCON.3) 0003 INT0 ( Pin 3.2 ) 0 1 2 IT0 Edge-triggered Level-triggered (default) IE1 (TCON.3) INT0 ( Pin 3.3 ) 0 1 2 IT1 Edge-triggered Level-triggered (default) 0013

ORG 0000H LJMP MAIN ; ;interrupt service routine (ISR) ;for hardware external interrupt INT1 ; ORG 0013H SETB P1.1 MOV R0,200 WAIT: DJNZ R0,WAIT CLR P1.1 RETI ; ;main program for initialization ; ORG 30H MAIN: SETB IT1 ;on negative edge of INT1 MOV IE,#10000100B WAIT2: SJMP WAIT2 END

 What if two interrupt sources interrupt at the same time?  The interrupt with the highest PRIORITY gets serviced first.  All interrupts have a power on default priority order. 1. External interrupt 0 (INT0) 2. Timer interrupt0 (TF0) 3. External interrupt 1 (INT1) 4. Timer interrupt1 (TF1) 5. Serial communication (RI+TI)  Priority can also be set to “high” or “low” by IP reg.

IP.7: reserved IP.6: reserved IP.5: timer 2 interrupt priority bit(8052 only) IP.4: serial port interrupt priority bit IP.3: timer 1 interrupt priority bit IP.2: external interrupt 1 priority bit IP.1: timer 0 interrupt priority bit IP.0: external interrupt 0 priority bit --- PX0 PT0 PX1 PT1 PS PT2 ---

 MOV IP , #00000100B or SETB IP.2 gives priority order 1. Int1 2. Int0 3. Timer0 4. Timer1 5. Serial  MOV IP , #00001100B gives priority order 1. Int1 2. Timer1 3. Int0 4. Timer0 5. Serial --- PX0 PT0 PX1 PT1 PS PT2 ---

Compiler Linker Programmer Sources Objects Binary

 Software resides in system non-volatile memory  External or internal flash/EEPROM/PROM memories  Modern microcontrollers are capable of writing the internal flash memory run-time and often do not have an external memory bus  Development is done outside the system  Cross-compilers are used to create binary files  Cross-compiler creates binary files for a different architecture than it is running on  Various commercial and free compilers available  System is programmed by uploading the binary In-system programming tools or external flashers

• Peripheral Interface Controller (PIC) was originally designed by General Instruments • In the late 1970s, GI introduced PIC® 1650 and 1655 – RISC with 30 instructions. • PIC was sold to Microchip • Features: low-cost, self-contained, 8-bit, Harvard structure, pipelined, RISC, single accumulator, with fixed reset and interrupt vectors.

PIC Family Stack Size Instruction Word Size No of Instructions Interrupt Vectors 12CX/12FX 2 12- or 14-bit 33 None 16C5X/16F5X 2 12-bit 33 None 16CX/16FX 8 14-bit 35 1 17CX 16 16-bit 58 4 18CX/18FX 32 16-bit 75 2 ‘C’ implies CMOS technology; Complementary Metal Oxide Semiconductor ‘F’ insert indicates incorporation of Flash memory technology Example: 16C84 was the first of its kind. It was later reissued as the 16F84, incorporating Flash memory technology. It was then reissued as 16F84A.

 Texas Instruments mixed- signal Microcontroller  16-bit RISC  ROM: 1-60 kB  RAM: Up to 10 kB  Analogue  12 bit ADC & DAC  LCD driver  Digital  USART x 2  DMA controller  Timers

 Atmel AVR family  8-bit RISC  RAM: Up to 4 kB  ROM: Up to 128 kB  Analogue  ADC  PWM  Digital  USARTs  Timers

 Recently embedded systems are being designed on a single chip, called system on chip (SoC). SoC is a new design innovation for embedded systems.  An embedded processor is a part of the SoC VLSI circuit

A SoC is embedded with the following components : o Multiple processors o Memories o Multiple standard source solutions (IP-Intellectual property) o Cores and o Other logic analog units o A SoC may also have a network protocol embedded in to it.

o It may embed an encryption function unit. o It can embed discrete cosine transforms for signal processing applications. o It may also embed FPGA cores (Field programmable Gate Array) o Recently exemplary GPPs called ARM 7, ARM 9 which embed onto a VLSI chip, have been developed by ARM & Texas Instruments.

To understand the design of a simple embedded system let us first consider the idea of a data acquisition system. The data acquisition system is shown in the next slide.

For example let me consider a simple case of temperature measurement embedded system.  First we must select a temperature sensor like thermistor or AD590 or LM35 or LM335 or LM75 etc.  After this the analog data is converted into digital data and at the same time proper signal conditioning is done.

 This digital input is fed to the microcontroller through its ports.  By developing a suitable program (Embedded C or Assembly) the data is processed and controlled.  For this purpose keil or Ride or IAR ARM Embedded workbench C compilers can be used.

 Once the program is debugged, and found error free it can be dumped into the microcontroller flash memory using ISP (Philips - Flash magic or any ISP).  Now, your microcontroller chip acts as an embedded chip.

For the sake of clarity I present the block diagram of a simple embedded system.

8051 Microcontroller architecture and operation

8051 Microcontroller architecture and operation

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