Stream helps developers build engaging apps that scale to millions with performant and flexible Chat, Feeds, Moderation, and Video APIs and SDKs powered by a global edge network and enterprise-grade infrastructure. Learn more →
Top 5 Haskell Verilog Projects
-
I thought that this was about the hardware description language Clash developed by some ex-colleagues, but it appeared to be something else. Clash [1] is based on the functional programming language Haskell and it can output to VHDL, Verilog, or SystemVerilog.
Although the last official release mentioned on the website is from 2021, it is still actively developed on GitHub [2]. See also contranomy [3] for a non-pipelined RV32I RISC-V core written in Clash.
[1] https://clash-lang.org/
[2] https://github.com/clash-lang/clash-compiler
[3] https://github.com/christiaanb/contranomy
-
Stream
Stream - Scalable APIs for Chat, Feeds, Moderation, & Video. Stream helps developers build engaging apps that scale to millions with performant and flexible Chat, Feeds, Moderation, and Video APIs and SDKs powered by a global edge network and enterprise-grade infrastructure.
-
-
Reduceron
FPGA Haskell machine with game changing performance. Reduceron is Matthew Naylor, Colin Runciman and Jason Reich's high performance FPGA softcore for running lazy functional programs, including hardware garbage collection. Reduceron has been implemented on various FPGAs with clock frequency ranging from 60 to 150 MHz depending on the FPGA. A high degree of parallelism allows Reduceron to implement graph evaluation very efficiently. This fork aims to continue development on this, with a view to
-
verismith
Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.
-
-
InfluxDB
InfluxDB – Built for High-Performance Time Series Workloads. InfluxDB 3 OSS is now GA. Transform, enrich, and act on time series data directly in the database. Automate critical tasks and eliminate the need to move data externally. Download now.
Haskell Verilog discussion
Haskell Verilog related posts
-
Verilog functions and wires
-
An addressable little explored language gap: HDL - Hardware Description Languages, any language used for electronic circuit design, description, and specs
-
A circuit simulator that doesn't look like it was made in 2003
-
HDL desugaring
-
please tell me I'm not the only twat who's ended up on this page
- A note from our sponsor - Stream getstream.io | 20 Dec 2025