Single Cycle Processor written in SystemVerilog for executing machine code of RISC-V ISA
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Apr 23, 2023 - SystemVerilog
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risc-v-architecture
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3-stage RISC-V Pipelined Processor with interrupt CSR support
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Jun 2, 2023 - SystemVerilog
A fully pipelined 5-stage RV32I processor implemented in SystemVerilog. This design models instruction-level parallelism with forwarding and hazard detection, and passes all RISCOF compliance tests for the RV32I base ISA.
processor-architecture fpga processor riscv rtl vivado systemverilog hdl risc-v rv32i verilator processor-design fpga-programming arty-a7 risc-v-architecture five-stage riscof pipelined-processor rv32i-processor
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Jul 27, 2025 - SystemVerilog
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