[AMDGPU][NPM] Port AMDGPUSetWavePriority to NPM

[optimisan]

No description provided.

[optimisan]

• [AMDGPU][NPM] Cleanup AMDGPUPassRegistry.def #130071
• [CodeGen][NPM] Port StackFrameLayoutAnalysisPass to NPM #130070
• [CodeGen][NPM] Port MachineSanitizerBinaryMetadata to NPM #130069
• [CodeGen][NPM] Port RemoveLoadsIntoFakeUses to NPM #130068
• [CodeGen][NPM] Port BranchRelaxation to NPM #130067
• [CodeGen][NPM] Port PostRAHazardRecognizer to NPM #130066
• [AMDGPU][NPM] Port SIPreEmitPeephole to NPM #130065
• [AMDGPU][NPM] Port AMDGPUSetWavePriority to NPM #130064 👈 (View in Graphite)
• [AMDGPU][NPM] Port SILateBranchLowering to NPM #130063
• [AMDGPU][NPM] Port SIInsertHardClauses to NPM #130062
• [AMDGPU][NPM] Port SIInsertWaitcnts to NPM #130061
• [AMDGPU][NPM] Port SIMemoryLegalizer to NPM #130060
• [AMDGPU][NPM] Port GCNCreateVOPD to NPM #130059
• [CodeGen][NPM] Port PatchableFunction to NPM #129866
• [CodeGen][NPM] Port XRayInstrumentation to NPM #129865
• [CodeGen][NPM] Port FEntryInserter to NPM #129857
• [CodeGen][NPM] Port MachineBlockPlacementStats to NPM #129853
• [CodeGen][NPM] Port MachineBlockPlacement to NPM #129828
• main

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[optimisan]

such cut-pasting for tests is liable to get damaged if legacy pipeline changes but will be replaced very soon (once whole NPM pipeline is in place)

[llvmbot]

@llvm/pr-subscribers-backend-amdgpu

Author: Akshat Oke (optimisan)

Changes

---

Full diff: https://github.com/llvm/llvm-project/pull/130064.diff

5 Files Affected:

• (modified) llvm/lib/Target/AMDGPU/AMDGPU.h (+8-1)
• (modified) llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def (+1-1)
• (modified) llvm/lib/Target/AMDGPU/AMDGPUSetWavePriority.cpp (+32-12)
• (modified) llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp (+2-3)
• (modified) llvm/test/CodeGen/AMDGPU/set-wave-priority.ll (+5)

diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.h b/llvm/lib/Target/AMDGPU/AMDGPU.h index d1dc62e9cc526..27ae6d42ec21d 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPU.h +++ b/llvm/lib/Target/AMDGPU/AMDGPU.h @@ -392,6 +392,13 @@ class SILateBranchLoweringPass static bool isRequired() { return true; } }; +class AMDGPUSetWavePriorityPass + : public PassInfoMixin<AMDGPUSetWavePriorityPass> { +public: + PreservedAnalyses run(MachineFunction &MF, + MachineFunctionAnalysisManager &MFAM); +}; + FunctionPass *createAMDGPUAnnotateUniformValuesLegacy(); ModulePass *createAMDGPUPrintfRuntimeBinding(); @@ -504,7 +511,7 @@ void initializeGCNPreRAOptimizationsLegacyPass(PassRegistry &); extern char &GCNPreRAOptimizationsID; FunctionPass *createAMDGPUSetWavePriorityPass(); -void initializeAMDGPUSetWavePriorityPass(PassRegistry &); +void initializeAMDGPUSetWavePriorityLegacyPass(PassRegistry &); void initializeGCNRewritePartialRegUsesLegacyPass(llvm::PassRegistry &); extern char &GCNRewritePartialRegUsesID; diff --git a/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def b/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def index 318aad5590cda..4956897d22fde 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def +++ b/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def @@ -100,6 +100,7 @@ MACHINE_FUNCTION_PASS("amdgpu-insert-delay-alu", AMDGPUInsertDelayAluPass()) MACHINE_FUNCTION_PASS("amdgpu-isel", AMDGPUISelDAGToDAGPass(*this)) MACHINE_FUNCTION_PASS("amdgpu-pre-ra-long-branch-reg", GCNPreRALongBranchRegPass()) MACHINE_FUNCTION_PASS("amdgpu-rewrite-partial-reg-uses", GCNRewritePartialRegUsesPass()) +MACHINE_FUNCTION_PASS("amdgpu-set-wave-priority", AMDGPUSetWavePriorityPass()) MACHINE_FUNCTION_PASS("amdgpu-pre-ra-optimizations", GCNPreRAOptimizationsPass()) MACHINE_FUNCTION_PASS("amdgpu-nsa-reassign", GCNNSAReassignPass()) MACHINE_FUNCTION_PASS("gcn-dpp-combine", GCNDPPCombinePass()) @@ -131,7 +132,6 @@ MACHINE_FUNCTION_PASS("si-wqm", SIWholeQuadModePass()) #define DUMMY_MACHINE_FUNCTION_PASS(NAME, CREATE_PASS) DUMMY_MACHINE_FUNCTION_PASS("amdgpu-pre-ra-optimizations", GCNPreRAOptimizationsPass()) DUMMY_MACHINE_FUNCTION_PASS("amdgpu-rewrite-partial-reg-uses", GCNRewritePartialRegUsesPass()) -DUMMY_MACHINE_FUNCTION_PASS("amdgpu-set-wave-priority", AMDGPUSetWavePriorityPass()) DUMMY_MACHINE_FUNCTION_PASS("si-pre-emit-peephole", SIPreEmitPeepholePass()) // TODO: Move amdgpu-preload-kern-arg-prolog to MACHINE_FUNCTION_PASS since it diff --git a/llvm/lib/Target/AMDGPU/AMDGPUSetWavePriority.cpp b/llvm/lib/Target/AMDGPU/AMDGPUSetWavePriority.cpp index c16d33f1453c0..29aecda82bc4b 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUSetWavePriority.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUSetWavePriority.cpp @@ -19,6 +19,7 @@ #include "SIInstrInfo.h" #include "llvm/ADT/PostOrderIterator.h" #include "llvm/CodeGen/MachineFunctionPass.h" +#include "llvm/CodeGen/MachinePassManager.h" using namespace llvm; @@ -40,15 +41,11 @@ struct MBBInfo { using MBBInfoSet = DenseMap<const MachineBasicBlock *, MBBInfo>; -class AMDGPUSetWavePriority : public MachineFunctionPass { +class AMDGPUSetWavePriority { public: static char ID; - AMDGPUSetWavePriority() : MachineFunctionPass(ID) {} - - StringRef getPassName() const override { return "Set wave priority"; } - - bool runOnMachineFunction(MachineFunction &MF) override; + bool run(MachineFunction &MF); private: MachineInstr *BuildSetprioMI(MachineBasicBlock &MBB, @@ -58,15 +55,30 @@ class AMDGPUSetWavePriority : public MachineFunctionPass { const SIInstrInfo *TII; }; +class AMDGPUSetWavePriorityLegacy : public MachineFunctionPass { +public: + static char ID; + + AMDGPUSetWavePriorityLegacy() : MachineFunctionPass(ID) {} + + StringRef getPassName() const override { return "Set wave priority"; } + + bool runOnMachineFunction(MachineFunction &MF) override { + if (skipFunction(MF.getFunction())) + return false; + return AMDGPUSetWavePriority().run(MF); + } +}; + } // End anonymous namespace. -INITIALIZE_PASS(AMDGPUSetWavePriority, DEBUG_TYPE, "Set wave priority", false, - false) +INITIALIZE_PASS(AMDGPUSetWavePriorityLegacy, DEBUG_TYPE, "Set wave priority", + false, false) -char AMDGPUSetWavePriority::ID = 0; +char AMDGPUSetWavePriorityLegacy::ID = 0; FunctionPass *llvm::createAMDGPUSetWavePriorityPass() { - return new AMDGPUSetWavePriority(); + return new AMDGPUSetWavePriorityLegacy(); } MachineInstr * @@ -96,12 +108,20 @@ static bool isVMEMLoad(const MachineInstr &MI) { return SIInstrInfo::isVMEM(MI) && MI.mayLoad(); } -bool AMDGPUSetWavePriority::runOnMachineFunction(MachineFunction &MF) { +PreservedAnalyses +llvm::AMDGPUSetWavePriorityPass::run(MachineFunction &MF, + MachineFunctionAnalysisManager &MFAM) { + if (!AMDGPUSetWavePriority().run(MF)) + return PreservedAnalyses::all(); + return getMachineFunctionPassPreservedAnalyses(); +} + +bool AMDGPUSetWavePriority::run(MachineFunction &MF) { const unsigned HighPriority = 3; const unsigned LowPriority = 0; Function &F = MF.getFunction(); - if (skipFunction(F) || !AMDGPU::isEntryFunctionCC(F.getCallingConv())) + if (!AMDGPU::isEntryFunctionCC(F.getCallingConv())) return false; const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp index b9d62cc9e4b63..857af30b348cb 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp @@ -2163,9 +2163,8 @@ void AMDGPUCodeGenPassBuilder::addPreEmitPass(AddMachinePass &addPass) const { addPass(SILateBranchLoweringPass()); - if (isPassEnabled(EnableSetWavePriority, CodeGenOptLevel::Less)) { - // TODO: addPass(AMDGPUSetWavePriorityPass()); - } + if (isPassEnabled(EnableSetWavePriority, CodeGenOptLevel::Less)) + addPass(AMDGPUSetWavePriorityPass()); if (TM.getOptLevel() > CodeGenOptLevel::None) { // TODO: addPass(SIPreEmitPeepholePass()); diff --git a/llvm/test/CodeGen/AMDGPU/set-wave-priority.ll b/llvm/test/CodeGen/AMDGPU/set-wave-priority.ll index ab6877ac4e6d1..a27d1217031ca 100644 --- a/llvm/test/CodeGen/AMDGPU/set-wave-priority.ll +++ b/llvm/test/CodeGen/AMDGPU/set-wave-priority.ll @@ -1,6 +1,11 @@ ; RUN: llc -mtriple=amdgcn -amdgpu-set-wave-priority=true -o - %s | \ ; RUN: FileCheck %s +; RUN: llc -mtriple=amdgcn -stop-after=si-late-branch-lowering -o - %s | \ +; RUN: llc -x mir -mtriple=amdgcn -passes=amdgpu-set-wave-priority -o - | \ +; RUN: llc -x mir -mtriple=amdgcn -start-after=si-late-branch-lowering -o - | \ +; RUN: FileCheck %s + ; CHECK-LABEL: no_setprio: ; CHECK-NOT: s_setprio ; CHECK: ; return to shader part epilog 

[optimisan]

fixed in 7c4009f