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author | PMR <pmr@pmr-lander> | 2020-07-21 07:10:57 +0000 |
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committer | PMR <pmr@pmr-lander> | 2020-07-21 07:10:57 +0000 |
commit | 5c62402a66f3735b25438fa56524e980e2d40307 (patch) | |
tree | 67c9276275f1b3eeb8dd3c56c92dd55f265c4bb2 | |
parent | 9a51344dcd8ad03105cb3fd3efd7211fd7c8fd86 (diff) | |
parent | 29ab050fe8e206810bf17345968c885dd7334eb0 (diff) |
Merge #387498 from ~kchsieh/plainbox-provider-checkbox/+git/plainbox-provider-checkbox:add-tgl-support
-rwxr-xr-x | bin/cpuid.py | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/bin/cpuid.py b/bin/cpuid.py index 6543dc4..36d5b46 100755 --- a/bin/cpuid.py +++ b/bin/cpuid.py @@ -74,6 +74,15 @@ _CDECL_32_OPC = [ is_64bit = ctypes.sizeof(ctypes.c_voidp) == 8 +# EAX bitmap explaination +# [31:28] Reserved +# [27:20] Extended Family +# [19:16] Extended Model +# [15:14] Reserved +# [13:12] Processor Type +# [11:8] Family +# [7:4] Model +# [3:0] Stepping CPUIDS = { "Amber Lake": ['0x806e9'], "AMD EPYC": ['0x800f12'], @@ -96,6 +105,7 @@ CPUIDS = { "Penryn": ['0x1067a'], "Sandy Bridge": ['0x206a', '0x206d6', '0x206d7'], "Skylake": ['0x406e3', '0x506e3', '0x50654', '0x50652'], + "Tiger Lake": ['0x806c1'], "Westmere": ['0x2065', '0x206c', '0x206f'], "Whisky Lake": ['0x806eb', '0x806ec'], } |