From 29ab050fe8e206810bf17345968c885dd7334eb0 Mon Sep 17 00:00:00 2001
From: Kai-Chuan Hsieh <kaichuan.hsieh@canonical.com>
Date: Thu, 16 Jul 2020 15:42:38 +0800
Subject: Add output support for Tiger Lake CPUID

---
 bin/cpuid.py | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/bin/cpuid.py b/bin/cpuid.py
index d0cdea9..9ccc2e0 100755
--- a/bin/cpuid.py
+++ b/bin/cpuid.py
@@ -75,6 +75,15 @@ _CDECL_32_OPC = [
 
 is_64bit = ctypes.sizeof(ctypes.c_voidp) == 8
 
+# EAX bitmap explaination
+# [31:28] Reserved
+# [27:20] Extended Family
+# [19:16] Extended Model
+# [15:14] Reserved
+# [13:12] Processor Type
+# [11:8]  Family
+# [7:4]   Model
+# [3:0]   Stepping
 CPUIDS = {
         "Amber Lake":       ['0x806e9'],
         "AMD EPYC":         ['0x800f12'],
@@ -96,6 +105,7 @@ CPUIDS = {
         "Penryn":           ['0x1067a'],
         "Sandy Bridge":     ['0x206a', '0x206d6', '0x206d7'],
         "Skylake":          ['0x406e3', '0x506e3', '0x50654', '0x50652'],
+        "Tiger Lake":       ['0x806c1'],
         "Westmere":         ['0x2065', '0x206c', '0x206f'],
         "Whisky Lake":      ['0x806eb', '0x806ec'],
         }
-- 
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