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add I2S and EDMA support for IMX9 platform #97777

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30b324c
west.yml: update hal_nxp to enable i.MX91 EDMA
yananyang-nxp Oct 17, 2025
56b3b95
drivers: dma: dma_mcux_edma: enable MMIO mapping
yananyang-nxp Jul 11, 2025
e6a6bbe
drivers: mcux_ccm_rev2: add SAI clock support for i.MX9 platform
yananyang-nxp Jul 11, 2025
6f6fec3
drivers: mcux_ccm_rev2: fix code format
Zhiqiang-Hou Oct 22, 2025
6abdcc3
drivers: i2s: mcux_sai: correct DMA burst length
Zhiqiang-Hou Oct 22, 2025
43556a5
drivers: i2s: i2s_mcux_sai: use device model MMIO mapping
yananyang-nxp Jul 11, 2025
30cbb25
drivers: i2s: mcux_sai: fix the type of var num_of_bufs
Zhiqiang-Hou Oct 22, 2025
e37c878
drivers: i2s: mcux_sai: set the Bit Clock Swap on the feature enabled
Zhiqiang-Hou Oct 22, 2025
cb46047
drivers: i2s: i2s_mcux_sai: add i.MX9 platform support
Zhiqiang-Hou Oct 22, 2025
79096cd
dts: arm64: imx93: add sai3_2 and edma4_2 node for i2s_mcux_sai driver
yananyang-nxp Jul 16, 2025
f829f03
boards: imx93_evk: add sai3_2 and edma4_2 node for i2s_mcux_sai driver
yananyang-nxp Jul 16, 2025
96d7a17
boards: frdm_imx93: add sai3_2 and edma4_2 node for i2s_mcux_sai driver
yananyang-nxp Jul 16, 2025
be32ffc
dts: arm64: imx9131: add sai3_2 and edma4_2 node for i2s_mcux_sai driver
yananyang-nxp Oct 15, 2025
bac888f
boards: frdm_imx91: add sai3_2 and edma4_2 node for i2s_mcux_sai driver
yananyang-nxp Jul 16, 2025
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15 changes: 15 additions & 0 deletions boards/nxp/frdm_imx91/frdm_imx91-pinctrl.dtsi
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Original file line number Diff line number Diff line change
Expand Up @@ -7,6 +7,21 @@
#include <nxp/nxp_imx/mimx9131cvvxj-pinctrl.dtsi>

&pinctrl {
sai3_default: sai3_default {
group0 {
pinmux = <&iomuxc1_gpio_io16_sai_tx_bclk_sai3_tx_bclk>,
<&iomuxc1_gpio_io17_sai_mclk_sai3_mclk>,
<&iomuxc1_gpio_io18_sai_rx_bclk_sai3_rx_bclk>,
<&iomuxc1_gpio_io19_sai_rx_sync_sai3_rx_sync>,
<&iomuxc1_gpio_io20_sai_rx_data_sai3_rx_data0>,
<&iomuxc1_gpio_io21_sai_tx_data_sai3_tx_data0>,
<&iomuxc1_gpio_io26_sai_tx_sync_sai3_tx_sync>;
bias-pull-up;
slew-rate = "slightly_fast";
drive-strength = "x4";
};
};

uart1_default: uart1_default {
group0 {
pinmux = <&iomuxc1_uart1_rxd_lpuart_rx_lpuart1_rx>,
Expand Down
10 changes: 10 additions & 0 deletions boards/nxp/frdm_imx91/frdm_imx91_mimx9131.dts
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Original file line number Diff line number Diff line change
Expand Up @@ -32,6 +32,16 @@
pinctrl-names = "default";
};

&edma4_2 {
status = "disabled";
};

&sai3_2 {
status = "disabled";
pinctrl-0 = <&sai3_default>;
pinctrl-names = "default";
};

&tpm2 {
status = "okay";
};
15 changes: 15 additions & 0 deletions boards/nxp/frdm_imx93/frdm_imx93-pinctrl.dtsi
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Original file line number Diff line number Diff line change
Expand Up @@ -71,6 +71,21 @@
};
};

sai3_default: sai3_default {
group0 {
pinmux = <&iomuxc1_gpio_io16_sai_tx_bclk_sai3_tx_bclk>,
<&iomuxc1_gpio_io17_sai_mclk_sai3_mclk>,
<&iomuxc1_gpio_io18_sai_rx_bclk_sai3_rx_bclk>,
<&iomuxc1_gpio_io19_sai_rx_sync_sai3_rx_sync>,
<&iomuxc1_gpio_io20_sai_rx_data_sai3_rx_data00>,
<&iomuxc1_gpio_io21_sai_tx_data_sai3_tx_data00>,
<&iomuxc1_gpio_io26_sai_tx_sync_sai3_tx_sync>;
bias-pull-up;
slew-rate = "slightly_fast";
drive-strength = "x4";
};
};

spi3_default: spi3_default {
group0 {
pinmux = <&iomuxc1_gpio_io07_lpspi_pcs_lpspi3_pcs1>,
Expand Down
6 changes: 6 additions & 0 deletions boards/nxp/frdm_imx93/frdm_imx93_mimx9352_a55.dts
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Original file line number Diff line number Diff line change
Expand Up @@ -146,6 +146,12 @@
status = "okay";
};

&sai3_2 {
status = "disabled";
pinctrl-0 = <&sai3_default>;
pinctrl-names = "default";
};

&wdog4 {
status = "okay";
};
Expand Down
13 changes: 13 additions & 0 deletions boards/nxp/imx93_evk/imx93_evk-pinctrl.dtsi
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Original file line number Diff line number Diff line change
Expand Up @@ -71,6 +71,19 @@
};
};

sai3_default: sai3_default {
group0 {
pinmux = <&iomuxc1_gpio_io16_sai_tx_bclk_sai3_tx_bclk>,
<&iomuxc1_gpio_io17_sai_mclk_sai3_mclk>,
<&iomuxc1_gpio_io19_sai_tx_data_sai3_tx_data00>,
<&iomuxc1_gpio_io20_sai_rx_data_sai3_rx_data00>,
<&iomuxc1_gpio_io26_sai_tx_sync_sai3_tx_sync>;
bias-pull-up;
slew-rate = "slightly_fast";
drive-strength = "x4";
};
};

spi3_default: spi3_default {
group0 {
pinmux = <&iomuxc1_gpio_io07_lpspi_pcs_lpspi3_pcs1>,
Expand Down
10 changes: 10 additions & 0 deletions boards/nxp/imx93_evk/imx93_evk_mimx9352_a55.dts
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Original file line number Diff line number Diff line change
Expand Up @@ -185,6 +185,10 @@
pinctrl-names = "default";
};

&edma4_2 {
status = "disabled";
};

&gpio1 {
status = "okay";
};
Expand All @@ -208,6 +212,12 @@
status = "okay";
};

&sai3_2 {
status = "disabled";
pinctrl-0 = <&sai3_default>;
pinctrl-names = "default";
};

&usdhc1 {
pinctrl-0 = <&pinmux_usdhc1>;
pinctrl-1 = <&pinmux_usdhc1_100mhz>;
Expand Down
56 changes: 52 additions & 4 deletions drivers/clock_control/clock_control_mcux_ccm_rev2.c
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Original file line number Diff line number Diff line change
Expand Up @@ -39,6 +39,13 @@ static int mcux_ccm_on(const struct device *dev,
case IMX_CCM_ENET1G_CLK:
CLOCK_EnableClock(ENET1G_CLOCK);
return 0;
#endif
#ifdef CONFIG_I2S_MCUX_SAI
#if defined(CONFIG_SOC_MIMX9352) || defined(CONFIG_SOC_MIMX9131) || defined(CONFIG_SOC_MIMX9111)
case IMX_CCM_SAI1_CLK:
CLOCK_EnableClock(kCLOCK_Sai1 + instance);
return 0;
#endif
#endif
default:
(void)instance;
Expand Down Expand Up @@ -124,13 +131,15 @@ static int mcux_ccm_get_subsys_rate(const struct device *dev,
#endif

#ifdef CONFIG_DMA_MCUX_EDMA_V4
#if !defined(CONFIG_SOC_MIMX9352) && !defined(CONFIG_SOC_MIMX9131) && !defined(CONFIG_SOC_MIMX9111)
case IMX_CCM_EDMA3_CLK:
clock_root = kCLOCK_Root_M33;
break;
case IMX_CCM_EDMA4_CLK:
clock_root = kCLOCK_Root_Wakeup_Axi;
break;
#endif
#endif

#ifdef CONFIG_PWM_MCUX
#if defined(CONFIG_SOC_SERIES_IMXRT118X)
Expand All @@ -157,19 +166,25 @@ static int mcux_ccm_get_subsys_rate(const struct device *dev,
#endif

#ifdef CONFIG_I2S_MCUX_SAI
#if (defined(CONFIG_SOC_MIMX9352) || defined(CONFIG_SOC_MIMX9131) || defined(CONFIG_SOC_MIMX9111))
case IMX_CCM_SAI1_CLK:
clock_root = kCLOCK_Root_Sai1;
clock_root = kCLOCK_Root_Sai1 + instance;
break;
#else
case IMX_CCM_SAI1_CLK:
clock_root = kCLOCK_Root_Sai1;
break;
case IMX_CCM_SAI2_CLK:
clock_root = kCLOCK_Root_Sai2;
clock_root = kCLOCK_Root_Sai2;
break;
case IMX_CCM_SAI3_CLK:
clock_root = kCLOCK_Root_Sai3;
clock_root = kCLOCK_Root_Sai3;
break;
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Please don't mix code cleanups with new feature. Create a separate patch for cleanups.
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Fixed in the updated PR. Thanks!
case IMX_CCM_SAI4_CLK:
clock_root = kCLOCK_Root_Sai4;
clock_root = kCLOCK_Root_Sai4;
break;
#endif
#endif

#ifdef CONFIG_ETH_NXP_ENET
case IMX_CCM_ENET_CLK:
Expand Down Expand Up @@ -372,6 +387,39 @@ static int CCM_SET_FUNC_ATTR mcux_ccm_set_subsys_rate(const struct device *dev,
return mipi_csi2rx_clock_set_freq(kCLOCK_Root_Csi2_Esc, clock_rate);
#endif

#if (defined(CONFIG_SOC_MIMX9352) || defined(CONFIG_SOC_MIMX9131) || \
defined(CONFIG_SOC_MIMX9111)) && defined(CONFIG_I2S_MCUX_SAI)
case IMX_CCM_SAI1_CLK:
case IMX_CCM_SAI2_CLK:
case IMX_CCM_SAI3_CLK:
uint32_t clock_root, instance;
clock_root_config_t saiClkCfg;
fracn_pll_init_t g_audioPllCfg;

instance = (clock_name & IMX_CCM_INSTANCE_MASK);
clock_root = kCLOCK_Root_Sai1 + instance;

/* Fixed AUDIO_PLL's frequency at 393216000 Hz */
#define AUDIO_PLL_CLK_FREQ 393216000
g_clockSourceFreq[kCLOCK_AudioPll1Out] = AUDIO_PLL_CLK_FREQ;
g_clockSourceFreq[kCLOCK_AudioPll1] = AUDIO_PLL_CLK_FREQ;
g_audioPllCfg.rdiv = 1;
g_audioPllCfg.mfi = 163;
g_audioPllCfg.mfn = 84;
g_audioPllCfg.mfd = 100;
g_audioPllCfg.odiv = 10;

CLOCK_PllInit(AUDIOPLL, &g_audioPllCfg);

saiClkCfg.clockOff = false;
saiClkCfg.mux = 1;
saiClkCfg.div = (AUDIO_PLL_CLK_FREQ + (clock_rate - 1)) / clock_rate;

CLOCK_SetRootClock(clock_root, &saiClkCfg);

return 0;
#endif

default:
/* Silence unused variable warning */
ARG_UNUSED(clock_rate);
Expand Down
11 changes: 7 additions & 4 deletions drivers/dma/dma_mcux_edma.c
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Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
/*
* Copyright 2020-2024 NXP
* Copyright 2020-2025 NXP
*
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@dbaluta dbaluta Oct 22, 2025 •
edited
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Please explain in the commit message why this entire change is needed.
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No functionality change, just updated to use the device model MMIO APIs.
* SPDX-License-Identifier: Apache-2.0
*/
Expand Down Expand Up @@ -47,7 +47,7 @@ typedef DMA_Type DMAx_Type;
#endif

struct dma_mcux_edma_config {
DMAx_Type *base;
DEVICE_MMIO_NAMED_ROM(edma_mmio);
#if defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT
DMAMUX_Type **dmamux_base;
#endif
Expand Down Expand Up @@ -91,6 +91,7 @@ struct call_back {
};

struct dma_mcux_edma_data {
DEVICE_MMIO_NAMED_RAM(edma_mmio);
struct dma_context dma_ctx;
struct call_back *data_cb;
atomic_t *channels_atomic;
Expand All @@ -99,7 +100,7 @@ struct dma_mcux_edma_data {
#define DEV_CFG(dev) \
((const struct dma_mcux_edma_config *const)dev->config)
#define DEV_DATA(dev) ((struct dma_mcux_edma_data *)dev->data)
#define DEV_BASE(dev) ((DMAx_Type *)DEV_CFG(dev)->base)
#define DEV_BASE(dev) ((DMAx_Type *)DEVICE_MMIO_NAMED_GET(dev, edma_mmio))

#define DEV_CHANNEL_DATA(dev, ch) \
((struct call_back *)(&(DEV_DATA(dev)->data_cb[ch])))
Expand Down Expand Up @@ -1013,6 +1014,8 @@ static int dma_mcux_edma_init(const struct device *dev)

LOG_DBG("INIT NXP EDMA");

DEVICE_MMIO_NAMED_MAP(dev, edma_mmio, K_MEM_CACHE_NONE | K_MEM_DIRECT_MAP);

#if defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT
uint8_t i;

Expand Down Expand Up @@ -1156,7 +1159,7 @@ static int dma_mcux_edma_init(const struct device *dev)
static __aligned(DMA_TCD_ALIGN_SIZE) EDMA_TCDPOOL_CACHE_ATTR edma_tcd_t \
dma_tcdpool##n[DT_INST_PROP(n, dma_channels)][CONFIG_DMA_TCD_QUEUE_SIZE];\
static const struct dma_mcux_edma_config dma_config_##n = { \
.base = (DMAx_Type *)DT_INST_REG_ADDR(n),\
DEVICE_MMIO_NAMED_ROM_INIT(edma_mmio, DT_DRV_INST(n)),\
DMAMUX_BASE_INIT(n) \
.dma_requests = DT_INST_PROP(n, dma_requests), \
.dma_channels = DT_INST_PROP(n, dma_channels), \
Expand Down
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