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![Introduction:- The MIPS Instruction Set Architecture:- The MIPS Architecture defines thirty-two, 32-bit general purpose registers. Register $r0 is hardwired and always contains the value zero. The CPU uses byte addressing for word accesses and must be aligned on a byte boundary divisible by four (0, 4, 8, …). MIPS only has three instruction types: I-type is used for the Load and Stores instructions, R-type is used for Arithmetic instructions, and J-type is used for the Jump instructions. MIPS is a load/store architecture, meaning that all operations are performed on operands held in the processor registers and the main memory can only be accessed through the load and store instructions (e.g lw, sw). A load instruction loads a value from memory into a register. A store instruction stores a value from a register to memory. The load and store instructions use the sum of the offset value in the address/immediate field and the base register in the $rs field to address the memory. Arithmetic instructions or R-type include: ALU Immediate (e.g. addi), three-operand (e.g. add, and, slt), and shift instructions (e.g. sll, srl). The J-type instructions are used for jump instructions (e.g. j). Branch instructions (e.g. beq, bne) are I-type instructions which use the addition of an offset value from the current address in the address/immediate field along with the program counter (PC) to compute the branch target address; this is considered PC relative addressing. MIPS Single-Cycle Processor:- The MIPS single-cycle processor performs the tasks of instruction fetch, instruction decode, execution, memory access and write-back all in one clock cycle. First the PC value is used as an address to index the instruction memory which supplies a 32-bit value of the next instruction to be executed. The instructions opcode field bits [31-26] are sent to a control unit to determine the type of instruction to execute. The type of instruction then determines which control signals are to be asserted and what function the ALU is to perform, thus decoding the instruction. The instruction register address fields $rs bits [25 - 21], $rt bits [20 - 16], and $rd bits [15-11] are used to address the register file. The register file supports two independent register reads and one register write in one clock cycle. The register file reads in the requested addresses and outputs the data values contained in these registers. These data values can then be operated on by the ALU whose operation is determined by the control unit to either compute a memory address (e.g. load or store), compute an arithmetic result (e.g. add, and or slt), or perform a compare (e.g. branch). If the instruction decoded is arithmetic, the ALU result must be written to a register. If the instruction decoded is a load or a store, the ALU result is then used to address the data memory. The final step writes the ALU result or memory value back to the register file.](https://image.slidesharecdn.com/computerarchitectureprojectreport-230325163856-22af79a8/75/Implementation-Of-MIPS-Single-Cycle-Processor-3-2048.jpg)
![Instruction Decode Unit:- The main function of the instruction decode unit is to use the 32-bit instruction provided from the previous instruction fetch unit to index the register file and obtain the register data values. This unit also sign extends instruction bits [15 - 0] to 32-bit. The logic elements to be implemented in VHDL include several multiplexors and the register file. Control Unit:- The control unit of the MIPS single-cycle processor examines the instruction opcode bits [31 – 26] and decodes the instruction to generate nine control signals to be used. The RegDst control signal determines which register is written to the register file. The Jump control signal selects the jump address to be sent to the PC. The Branch control signal is used to select the branch address to be sent to the PC. The MemRead control signal is asserted during a load instruction when the data memory is read to load a register with its memory contents. The MemtoReg control signal determines if the ALU result or the data memory output is written to the register file. The ALUOp control signals determine the function the ALU performs. (e.g. and, or, add, sbu, slt) The MemWrite control signal is asserted when during a store instruction when a registers value is stored in the data memory. The ALUSrc control signal determines if the ALU second operand comes from the register file or the sign extend. The RegWrite control signal is asserted when the register file needs to be written.](https://image.slidesharecdn.com/computerarchitectureprojectreport-230325163856-22af79a8/75/Implementation-Of-MIPS-Single-Cycle-Processor-6-2048.jpg)
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Implementation Of MIPS Single Cycle Processor
This document reports on the implementation of a MIPS single-cycle processor at the Indian Institute of Space Science and Technology. It covers the MIPS architecture, instruction types, the design of the processor components including the register file, instruction fetch unit, control unit, execution unit, and data memory unit, as well as a testbench program demonstrating functionality. The implementation was successfully verified through simulation using ModelSim.
Implementation Of MIPS Single Cycle Processor
- 1. Indian Institute ofSpace Science and Technology Department of Avionics AV242 VLSI Design Lab Project Report on Implementation Of MIPS Single Cycle Processor Submitted by D. Pramod Reddy SC12B079 Date: 12/5/2014
- 2. Acknowledgement I take thisopportunity to express my gratitude towards Dr. Priyadarshanam sir and Nidheesh Ravi sir for assisting me through the project and also thanks to the Dept. of Avionics of the Indian Institute of Space Science and Technology for providing necessary support and facilities whenever needed.
- 3. Introduction:- The MIPS InstructionSet Architecture:- The MIPS Architecture defines thirty-two, 32-bit general purpose registers. Register $r0 is hardwired and always contains the value zero. The CPU uses byte addressing for word accesses and must be aligned on a byte boundary divisible by four (0, 4, 8, …). MIPS only has three instruction types: I-type is used for the Load and Stores instructions, R-type is used for Arithmetic instructions, and J-type is used for the Jump instructions. MIPS is a load/store architecture, meaning that all operations are performed on operands held in the processor registers and the main memory can only be accessed through the load and store instructions (e.g lw, sw). A load instruction loads a value from memory into a register. A store instruction stores a value from a register to memory. The load and store instructions use the sum of the offset value in the address/immediate field and the base register in the $rs field to address the memory. Arithmetic instructions or R-type include: ALU Immediate (e.g. addi), three-operand (e.g. add, and, slt), and shift instructions (e.g. sll, srl). The J-type instructions are used for jump instructions (e.g. j). Branch instructions (e.g. beq, bne) are I-type instructions which use the addition of an offset value from the current address in the address/immediate field along with the program counter (PC) to compute the branch target address; this is considered PC relative addressing. MIPS Single-Cycle Processor:- The MIPS single-cycle processor performs the tasks of instruction fetch, instruction decode, execution, memory access and write-back all in one clock cycle. First the PC value is used as an address to index the instruction memory which supplies a 32-bit value of the next instruction to be executed. The instructions opcode field bits [31-26] are sent to a control unit to determine the type of instruction to execute. The type of instruction then determines which control signals are to be asserted and what function the ALU is to perform, thus decoding the instruction. The instruction register address fields $rs bits [25 - 21], $rt bits [20 - 16], and $rd bits [15-11] are used to address the register file. The register file supports two independent register reads and one register write in one clock cycle. The register file reads in the requested addresses and outputs the data values contained in these registers. These data values can then be operated on by the ALU whose operation is determined by the control unit to either compute a memory address (e.g. load or store), compute an arithmetic result (e.g. add, and or slt), or perform a compare (e.g. branch). If the instruction decoded is arithmetic, the ALU result must be written to a register. If the instruction decoded is a load or a store, the ALU result is then used to address the data memory. The final step writes the ALU result or memory value back to the register file.
- 4. MIPS Single Clockcycle Implementation Implementation:- Register file:- The register file has two read and one write input ports, meaning that during one clock cycle, the processor must be able to read two independent data values and write a separate value into the register file. The register file was implemented in VHDL by declaring it as a one-dimensional array of 32 elements or registers each 8-bits wide. (e.g. TYPE register_file IS ARRAY (0 TO 31) OF STD_LOGIC_VECTOR (7 DOWNTO 0) ). By declaring the register file as a one-dimensional array, the requested register address would need to be converted into an integer to index the register file.(e.g. Read_Data_1 <= register_file ( CONV_INTEGER (read_register_address1 (4 DOWNTO 0))) ) Finally, to save from having to load each register with a value, the registers get initialized to their respective register number when the Reset signal is asserted. (e.g. $r1 = 1, $r2 = 2, etc.)
- 5. Register File Instruction FetchUnit:- The function of the instruction fetch unit is to obtain an instruction from the instruction memory using the current value of the PC and increment the PC value for the next instruction. Since this design uses an 8-bit data width we had to implement byte addressing to access the registers and word address to access the instruction memory. The instruction fetch component contains the following logic elements that are implemented in VHDL: 32-bit program counter (PC) register, an adder to increment the PC by four, the instruction memory, a multiplexor, and an AND gate used to select the value of the next PC. Instruction fetch stage
- 6. Instruction Decode Unit:- Themain function of the instruction decode unit is to use the 32-bit instruction provided from the previous instruction fetch unit to index the register file and obtain the register data values. This unit also sign extends instruction bits [15 - 0] to 32-bit. The logic elements to be implemented in VHDL include several multiplexors and the register file. Control Unit:- The control unit of the MIPS single-cycle processor examines the instruction opcode bits [31 – 26] and decodes the instruction to generate nine control signals to be used. The RegDst control signal determines which register is written to the register file. The Jump control signal selects the jump address to be sent to the PC. The Branch control signal is used to select the branch address to be sent to the PC. The MemRead control signal is asserted during a load instruction when the data memory is read to load a register with its memory contents. The MemtoReg control signal determines if the ALU result or the data memory output is written to the register file. The ALUOp control signals determine the function the ALU performs. (e.g. and, or, add, sbu, slt) The MemWrite control signal is asserted when during a store instruction when a registers value is stored in the data memory. The ALUSrc control signal determines if the ALU second operand comes from the register file or the sign extend. The RegWrite control signal is asserted when the register file needs to be written.
- 7. Control Unit Execution Unit:- Theexecution unit of the MIPS processor contains the arithmetic logic unit (ALU) which performs the operation determined by the ALUop signal. The branch address is calculated by adding the PC+4 to the sign extended immediate field shifted left 2 bits by a separate adder. The logic elements to be implemented in VHDL include a multiplexor, an adder, the ALU and the ALU control.
- 8. Data Memory Unit:- Thedata memory unit is only accessed by the load and store instructions. The load instruction asserts the Mem Read signal and uses the ALU Result value as an address to index the data memory. The read output data is then subsequently written into the register file. A store instruction asserts the Mem Write signal and writes the data value previously read from a register into the computed memory address. Following are used in implementing MIPS processor 1. Instruction memory and data memory are given byte addressing. 2. Since instruction and data memory are byte addressing program counter has to be incremented by 4 to fetch next instruction in instruction memory. 3. Little endian is used in implementation. 4. All the instructions are given in test bench in the form of decoded 32 bit data for each instruction. 5. Default contents in instruction and data memory are given to “0”.
- 9. TestBench Program:- addi $1,$0,11; $1=0B addi $2,$0,6 ; $2=6 loop: sub $1,$1,$2 ; $1=$1-$2=5 slt $3,$1,$2 ; $1<$2 so $3 = 1 beq $0,$1,loop ;$0=0,$1=1 so not equal hence don’t branch (loop=-12) add $1,$1,$2 ;$1=$1+$2=5+6=0B (11) over: beq $0,$0,over ; $0=$0 so loop over (over=-4) ModelSim Simulation:- Conclusion:- Hence the single clock cycle MIPS Processor is implemented and the result obtained by ModelSim shows the same result as traced above, therefore we can conclude that it is implemented successfully.