Presented by : Srishti Jain (cs - A) V sem
FPGA :- A Field Programmable Gate Array (FPGA) is a Programmable Logic Device(PLD) with higher densities and capable of implementing different functions in a short period of time. Topics covered:- • FPGA Overview • FPGA in detail • Programming Methodology
FPGA overview  2-D array of logic blocks and flip-flops with programmable interconnections.  Compact design  User can configure  Intersections between the logic blocks  The function of each block
FPGA in detail:  Logic blocks:  has an undefined function at the time of manufacture. before use, it must be programmed (i. e. reconfigured).  Contains-  Look-Up-Table(LUT)  Multiplexer  Flip-flop  Can be programmed to function as  Transistor  Microprocessor  Any combination of combinational and sequential logic functions to be continue..
 INTER CONNECTIONS  Are electrically programmable interconnection between the logic blocks.  Also contains electrically programmable switches.  A hierarchy of interconnect allows logic blocks to be interconnected as per system designer. Like one chip programmable breadboard.
Programming Methodology  Electrically programmable switches are used to program FPGA  Properties of programmable switch determine on- resistance, parasitic capacitance, volatility, reprogrammability, size etc.  Desired properties:  Minimum area consumption  Low on resistance; High off resistance  Low parasitic capacitance to the attached wire  Reliability in volume production  Various programming techniques are:-  SRAM programming technology  Antifuse programming technology  EPROM /EEPROM programming technology
SRAM Programming Technology  Employs SRAM (Static RAM) cells to control pass transistors and/or transmission gates  SRAM cells control the configuration of logic block as well  Volatile  Needs an external storage  Needs a power-on configuration mechanism  In-circuit re-programmable  Lesser configuration time  Occupies relatively larger area
Anti-fuse Programming Technology  Though implementation differ, all anti-fuse programming elements share common property  Uses materials which normally resides in high impedance state  But can be fused irreversibly into low impedance state by applying high voltage
 Very low ON Resistance (Faster implementation of circuits)  Limited size of anti-fuse elements; Interconnects occupy relatively lesser area  Offset : Larger transistors needed for programming  One Time Programmable  Cannot be re-programmed  (Design changes are not possible)  Retain configuration after power off
EPROM Programming Technology  EPROM Programming Technology  Two gates: Floating and Select  Normal mode:  No charge on floating gate  Transistor behaves as normal n-channel transistor  Floating gate charged by applying high voltage  Threshold of transistor (as seen by gate) increases  Transistor turned off permanently  Re-programmable by exposing to UV radiation
EPROM transistor EPROM memory cell
 No external storage mechanism  Re-programmable (Not all!)  Not in-system re-programmable  Re-programming is a time consuming task  An EPROM cell is erased by discharging the electrons on that cell’s floating gate.  The energy required to discharge the electrons is provided by a source of ultraviolet (UV) radiation.
EEPROM Programming Technology  Two gates: Floating and Select  Functionally equivalent to EPROM; Construction and structure differ  Electrically Erasable: Re-programmable by applying high voltage (No UV radiation expose!)  When un-programmed, the threshold (as seen by select gate) is negative!
summary
Other FPGA Advantages  Manufacturing cycle for ASIC is very costly, lengthy and engages lots of manpower  Mistakes not detected at design time have large impact on development time and cost  FPGAs are perfect for rapid prototyping of digital circuits  Easy upgrades like in case of software  Unique applications
Why better ?  FPGA programmed using electrically programmable switches  Routing architectures are complex.  Logic is implemented using multiple levels of lower fan-in gates.  Shorter time to market  Ability to re-program in the field to fix bugs FPGA DISADVANTAGE  FPGAs are generally slower than their application- specific integrated circuit (ASIC)  Can't handle as complex a design, and draw more power.
Application  Reconfigurable computing.  Applications of FPGAs include DSP, software-defined radio.  The inherent parallelism of the logic resources on the FPGA allows for considerable compute throughput.
FPGA Design and Programming  To define the behavior of the FPGA the user provides a hardware description language (HDL) or a schematic design.  Then, using an electronic design automation tool, a technology- mapped net list is generated.  The netlist can then be fitted to the actual FPGA architecture using a process called place-and-route.  The user will validate the map, place and route results via timing analysis, simulation, and other verification methodologies.  Once the design and validation process is complete, the binary file generated used to configure the FPGA.
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Fpga intro1

  • 1.
    Presented by : SrishtiJain (cs - A) V sem
  • 2.
    FPGA :- A Field Programmable Gate Array (FPGA) is a Programmable Logic Device(PLD) with higher densities and capable of implementing different functions in a short period of time. Topics covered:- • FPGA Overview • FPGA in detail • Programming Methodology
  • 3.
    FPGA overview  2-Darray of logic blocks and flip-flops with programmable interconnections.  Compact design  User can configure  Intersections between the logic blocks  The function of each block
  • 4.
    FPGA in detail: Logic blocks:  has an undefined function at the time of manufacture. before use, it must be programmed (i. e. reconfigured).  Contains-  Look-Up-Table(LUT)  Multiplexer  Flip-flop  Can be programmed to function as  Transistor  Microprocessor  Any combination of combinational and sequential logic functions to be continue..
  • 5.
     INTER CONNECTIONS  Are electrically programmable interconnection between the logic blocks.  Also contains electrically programmable switches.  A hierarchy of interconnect allows logic blocks to be interconnected as per system designer. Like one chip programmable breadboard.
  • 6.
    Programming Methodology  Electricallyprogrammable switches are used to program FPGA  Properties of programmable switch determine on- resistance, parasitic capacitance, volatility, reprogrammability, size etc.  Desired properties:  Minimum area consumption  Low on resistance; High off resistance  Low parasitic capacitance to the attached wire  Reliability in volume production  Various programming techniques are:-  SRAM programming technology  Antifuse programming technology  EPROM /EEPROM programming technology
  • 7.
    SRAM Programming Technology  EmploysSRAM (Static RAM) cells to control pass transistors and/or transmission gates  SRAM cells control the configuration of logic block as well  Volatile  Needs an external storage  Needs a power-on configuration mechanism  In-circuit re-programmable  Lesser configuration time  Occupies relatively larger area
  • 8.
    Anti-fuse Programming Technology  Thoughimplementation differ, all anti-fuse programming elements share common property  Uses materials which normally resides in high impedance state  But can be fused irreversibly into low impedance state by applying high voltage
  • 9.
     Very lowON Resistance (Faster implementation of circuits)  Limited size of anti-fuse elements; Interconnects occupy relatively lesser area  Offset : Larger transistors needed for programming  One Time Programmable  Cannot be re-programmed  (Design changes are not possible)  Retain configuration after power off
  • 10.
    EPROM Programming Technology  EPROM Programming Technology  Two gates: Floating and Select  Normal mode:  No charge on floating gate  Transistor behaves as normal n-channel transistor  Floating gate charged by applying high voltage  Threshold of transistor (as seen by gate) increases  Transistor turned off permanently  Re-programmable by exposing to UV radiation
  • 11.
  • 12.
     No externalstorage mechanism  Re-programmable (Not all!)  Not in-system re-programmable  Re-programming is a time consuming task  An EPROM cell is erased by discharging the electrons on that cell’s floating gate.  The energy required to discharge the electrons is provided by a source of ultraviolet (UV) radiation.
  • 13.
    EEPROM Programming Technology  Twogates: Floating and Select  Functionally equivalent to EPROM; Construction and structure differ  Electrically Erasable: Re-programmable by applying high voltage (No UV radiation expose!)  When un-programmed, the threshold (as seen by select gate) is negative!
  • 14.
  • 15.
    Other FPGA Advantages Manufacturing cycle for ASIC is very costly, lengthy and engages lots of manpower  Mistakes not detected at design time have large impact on development time and cost  FPGAs are perfect for rapid prototyping of digital circuits  Easy upgrades like in case of software  Unique applications
  • 16.
    Why better ? FPGA programmed using electrically programmable switches  Routing architectures are complex.  Logic is implemented using multiple levels of lower fan-in gates.  Shorter time to market  Ability to re-program in the field to fix bugs FPGA DISADVANTAGE  FPGAs are generally slower than their application- specific integrated circuit (ASIC)  Can't handle as complex a design, and draw more power.
  • 17.
    Application  Reconfigurable computing.  Applications of FPGAs include DSP, software-defined radio.  The inherent parallelism of the logic resources on the FPGA allows for considerable compute throughput.
  • 18.
    FPGA Design andProgramming  To define the behavior of the FPGA the user provides a hardware description language (HDL) or a schematic design.  Then, using an electronic design automation tool, a technology- mapped net list is generated.  The netlist can then be fitted to the actual FPGA architecture using a process called place-and-route.  The user will validate the map, place and route results via timing analysis, simulation, and other verification methodologies.  Once the design and validation process is complete, the binary file generated used to configure the FPGA.
  • 19.