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![Scientific Journal Impact Factor (SJIF): 1.711 International Journal of Modern Trends in Engineering and Research www.ijmter.com @IJMTER-2014, All rights Reserved 1 e-ISSN: 2349-9745 p-ISSN: 2393-8161 FPGA Implementation of High Speed Architecture of CSLA using D-Latches P.Sajid Khan1 , MD.Shamshad begum2 1 (M.tech_VLSI/SD), 2 M.Tech Assistant.Professor Dept.of E.C.E 1,2 ECE, Nimra college of Engineering and technology Abstract— Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing processors to perform fast arithmetic functions. The CSLA is used in many systems to overcome the problem of carry propagation delay by independently generating multiple carries and then select a carry to generate the sum. But the CSLA is not area efficient because it uses multiple pairs of Ripple Carry Adders (RCA). Due to the rapidly growing mobile industry not only the faster arithmetic unit but also less area and low power arithmetic units are needed. The modified CSLA architecture has developed using Binary to Excess-1 converter (BEC). This paper proposes an efficient method which replaces the BEC using D latch. Designs were developed using structural VHDL and synthesized in Xilinx 13.2 with reference to FPGA device XC3S500E. Keywords: Field Programmable Gate Array (FPGA), D-Latch, Area efficient, Carry Select Adder (CSLA), Square-root CSLA (SQRT CSLA). I. INTRODUCTION Design of area efficient high speed data path logic systems are one of the most essential areas of research in VLSI. In digital adders, the speed of addition is controlled by the time required to propagate a carry through the adder. The sum for each bit position in an elementary adder is generated sequentially only after the previous bit position was summed and a carry propagated into the next position. Bedriji proposed [1] that the problem of carry propagation delay is overcome by independently generating multiple radix carries and using this carries to select between simultaneously generated sums. Akhilash Tyagi introduced a scheme to generate carry bits with block carry in 1 from the carries of a block with block carry in 0 [4]. Chang and Hsiao proposed [3] that instead of using dual Ripple Carry Adder a Carry Select Adder scheme using an add one circuit to replace one RCA. Youngioon Kim and Lee Sup Kim introduced a multiplexer based add one circuit was proposed to reduce the area with negligible speed penalty. Yajuan He et al proposed an area efficient Square-root CSLA (SQRT CSLA) scheme based on a new first zero detection logic [9]. Ramkumar et al proposed a Binary to Excess-1 Converter (BEC) method to reduce the maximum delay of carry propagation in final stage of carry save adder [2]. Ramkumar and Harish proposed [8] BEC technique, which is a simple and efficient gate level modification to significantly reduce the area of SQRT CSLA. Padma Devi et al proposed [10] modified CSLA designed in different stages which reduces the area. CSLA is used in many computational systems to relieve the problem of carry propagation delay by independently generating multiple carries and then select a carry to generate the sum [1].However, the CSLA is not area efficient because it uses multiple pairs of RCA to generate partial sum and carry by considering carry in 0 and carry in 1, then the final sum and carry are selected by the multiplexers (Mux).The basic idea of this work is to use BEC instead of RCA with carry in 1 in the regular CSLA to achieve lower area [2], [3] and [4]. The main benefit of BEC](https://image.slidesharecdn.com/fpga-implementation-of-high-speed-architecture-of-csla-using-d-latches-150912102531-lva1-app6892/75/FPGA-Implementation-of-High-Speed-Architecture-of-CSLA-using-D-Latches-1-2048.jpg)
![International Journal of Modern Trends in Engineering and Research (IJMTER) Volume 01, Issue 06, [December - 2014] e-ISSN: 2349-9745, p-ISSN: 2393-8161 @IJMTER-2014, All rights Reserved 2 comes from the lesser number of logic gates than the n-bit Full Adder (FA). The details of BEC are discussed in section III. Section II also deals with the area evaluation methodology of the basic adder blocks and presents the detailed structure and the function of the BEC. The CSLA has been chosen for comparison with the proposed design as it has a lower area [5], [6]. The area evaluation methodology of the regular Linear CSLA and modified Linear CSLA are presented in section IV. The area evaluation methodology of the regular SQRT CSLA and modified SQRT CSLA are presented in section V. The FPGA implementation details and results are analyzed in section VI. Finally this work is concluded in section VII. II. AREA EVALUATION METHODOLOGY OF THE BASIC ADDER BLOCKS An XOR gate is shown in Fig. 1, which is implemented by using AND, OR and Inverter (NOT). The gates between the dotted lines are performing the operations in parallel. The area evaluation methodology considers all gates to be made up of AND, OR and Inverter (AOI), each having are The area evaluation is done by counting the total gates required for each logic block. Based on the CSLA blocks of 2:1 Mux, Half Adder (Hevaluated and listed in Table I). Fig1. Area evaluation of an XoR gate CSLA AREA COUNTXOR 5 2:1 MUX 4 HA 6 FA 13 Table 1: Area count of the Basic Blocks of CSLA III. BINARY TO EXCESS-1 CONVERTER (BEC) The main idea of this work is to use BEC with carry in=1 in order to reduce the area of t CSLA as well as regular SQRT CSLA. To RCA, an n+1-bit BEC is required. A structure of 3-bit BEC are shown in Fig. 2 and Table II, Boolean expressions for 3-bit BEC is shown functional symbols ~ NOT, & AND, ^ XOR) X0 = ~ B0 (1) X1 = B0 ^ B1 (2) X2 = B2 ^ (B0 & B1) (3)](https://image.slidesharecdn.com/fpga-implementation-of-high-speed-architecture-of-csla-using-d-latches-150912102531-lva1-app6892/75/FPGA-Implementation-of-High-Speed-Architecture-of-CSLA-using-D-Latches-2-2048.jpg)
![International Journal of Modern Trends in Engineering and Research (IJMTER) Volume 01, Issue 06, [December - 2014] e-ISSN: 2349-9745, p-ISSN: 2393-8161 @IJMTER-2014, All rights Reserved 3 Fig2: 3 –bit BEC Table 2: Functional table of 3 bit BEC IV. AREA EVALUATION METHODOLOGY OF REGULAR 16-BIT LINEAR AS WELL AS SQRT CSLA The structure of the 16-bit regular Linear CSLA is shown in Fig. 3. It has 4 groups of same size CA. Each group contains dual RCA and Mux. It accomplishes the addition by adding small portions of bits (each of equal size) and wait for the carry to complete the calculation. Both sum and carry are calculated for both possible solutions. The Linear carry select adder is constructed by chaining a number of equal length adder stages. Here the equal size of inputs is given to each block of the adder. The steps leading to the evaluations are given here. In the regular Linear CSLA, the group2 has two sets of 4-bit RCA. The selection input of 10:5 Mux is c3.If the c3=0, the mux select first RCA output otherwise it select second RCA output. The output of group2 is Sum [7:4] and carryout, c7.Then the area count of group2 is determined as follows Gate count = 117 (FA+HA+MUX) FA = 91 (7 * 13) HA = 6 (1 * 6) Mux = 20 (5 * 4) Similarly the estimated area of the other groups in the regular Linear CSLA are evaluated and listed in Table III Fig3: 16 bit Regular linear CSLA GROUP AREA B[2:0] X[2:0] 000 001 001 010 010 011 011 100 100 101 101 110 110 111 111 000](https://image.slidesharecdn.com/fpga-implementation-of-high-speed-architecture-of-csla-using-d-latches-150912102531-lva1-app6892/75/FPGA-Implementation-of-High-Speed-Architecture-of-CSLA-using-D-Latches-3-2048.jpg)
![International Journal of Modern Trends in Engineering and Research (IJMTER) Volume 01, Issue 06, [December - 2014] e-ISSN: 2349-9745, p-ISSN: 2393-8161 @IJMTER-2014, All rights Reserved 4 GROUP1 52 GROUP2 117 GROUP3 117 GROUP4 117 Table 3: Area count of the 16-bit regular linear CSLA groups The structure of the 16-bit regular SQRT CSLA is Shown in Fig. 4. It has 5 groups of different size RCA. Each group contains dual RCA and Mux. The linear carry select adder has two disadvantages there are high area usage and high time delay. These disadvantages of linear carry select adder can be rectified by SQRT CSLA. It is an improved one of linear CSLA. The time delay of the linear adder can decrease by having one more input into each set of adders than in the previous set. This is called a Square Root Carry Select Adder. Square Root carry select adder is constructed by equalizing the delay through two carry chains and the block-multiplexer signal from previous stage. The steps leading to the evaluations are given here. In the regular SQRT CSLA, the group2 has two sets of 2- bit RCA. The selection input of 3:2 Mux is c1. If the c1 = 0, the Mux select first RCA output otherwise it select second RCA output. The output of group2 are Sum [3:2] and carryout, c3. Then the area count of group2 is determined as follows: Gate count = 57 (FA + HA + Mux) FA = 39 (3 * 13) HA = 6 (1 * 6) Mux = 12 (3 * 4) Similarly the estimated area of the other groups in the regular SQRT CSLA are evaluated and listed in Table IV. GROUP AREA COUNT GROUP1 26 GROUP2 57 GROUP3 87 GROUP4 117 GROUP5 147 Table 4: Area count of the 16-bit regular sqrt CSLA groups](https://image.slidesharecdn.com/fpga-implementation-of-high-speed-architecture-of-csla-using-d-latches-150912102531-lva1-app6892/75/FPGA-Implementation-of-High-Speed-Architecture-of-CSLA-using-D-Latches-4-2048.jpg)
![International Journal of Modern Trends in Engineering and Research (IJMTER) Volume 01, Issue 06, [December - 2014] e-ISSN: 2349-9745, p-ISSN: 2393-8161 @IJMTER-2014, All rights Reserved 5 V. AREA EVALUATION METHODOLOGY OF MODIFIED 16-BIT LINEAR AS WELL AS SQRT CSLA The structure of the proposed 16-bit Linear and SQRT CSLA using BEC for RCA with carry in = 1 to optimize the area is shown in Fig. 5 and Fig. 6 respectively. The 16-bit modified Linear CSLA has 4 groups of same size RCA and BEC. Each group contains one RCA, one BEC and Mux. In the modified Linear CSLA, the group2 has one 4-bit RCA which has 3 FA and 1 HA for carry in = 0. Instead of another 4-bit RCA with carry in = 1 a 5-bit BEC is used which adds one to the output from 4-bit RCA. The selection input of 10:5 Mux is c3. If the c3 = 0, the Mux select RCA output otherwise it select BEC output. The output of group2 are Sum [7:4] and carryout, c7. Then the area count of group2 is determined as follows: Gate count = 89 (FA + HA + Mux + BEC) FA = 39 (3 * 13) HA = 6 (1 * 6) Mux = 20 (5 * 4) NOT = 1 AND = 3 (3 * 1) XOR = 20 (4 * 5) BEC (5-BIT) = NOT + AND + XOR = 24 Similarly the estimated area of the other groups in the modified Linear CSLA are evaluated and listed in Table V.](https://image.slidesharecdn.com/fpga-implementation-of-high-speed-architecture-of-csla-using-d-latches-150912102531-lva1-app6892/75/FPGA-Implementation-of-High-Speed-Architecture-of-CSLA-using-D-Latches-5-2048.jpg)
![International Journal of Modern Trends in Engineering and Research (IJMTER) Volume 01, Issue 06, [December - 2014] e-ISSN: 2349-9745, p-ISSN: 2393-8161 @IJMTER-2014, All rights Reserved 6 Table 5: Area count of the 16-bit modified linear CSLA groups The structure of the 16-bit modified SQRT CSLA is shown in Fig. 6. It has 5 groups of different size RCA and BEC. Each group contains one RCA, one BEC and MUX. In the modified SQRT CSLA, the group2 has one 2-bit RCA which has 1 FA and 1 HA for carry in = 0. Instead of another 2-bit RCA with carry in = 1 a 3-bit BEC is used which adds one to the output from 2-bit RCA. The selection input of 6:3 Mux is c3. If the c3 = 0, the Mux select RCA output otherwise it select BEC output. The output of group2 are Sum [3:2] and carryout,c3. Then the area count of group2 is determined as follows: Gate count = 43 (FA + HA + Mux + BEC) FA = 13 (1 * 13) HA = 6 (1 * 6) Mux = 12 (3 * 4) NOT = 1 AND = 1 XOR = 10 (2 * 5) BEC (3-BIT) = NOT + AND + XOR = 12 Similarly the estimated area of the other groups in the modified SQRT CSLA are evaluated and listed in Table VI. Table 6: Area count of the 16-bit modified sqrt CSLA groups](https://image.slidesharecdn.com/fpga-implementation-of-high-speed-architecture-of-csla-using-d-latches-150912102531-lva1-app6892/75/FPGA-Implementation-of-High-Speed-Architecture-of-CSLA-using-D-Latches-6-2048.jpg)
![International Journal of Modern Trends in Engineering and Research (IJMTER) Volume 01, Issue 06, [December - 2014] e-ISSN: 2349-9745, p-ISSN: 2393-8161 @IJMTER-2014, All rights Reserved 7 Comparing Tables III and IV with Tables V and VI, it is clear that the proposed modified Linear as well as SQRT CSLA save 84 gate and 97 gate areas than the regular Linear CSLA and regular SQRT CSLA respectively. VI. MODIFIED 16-BIT CSLA USING D-LATCH This method replaces the BEC add one circuit by D-latch with enable signal. Latches are used to store one bit information. Their outputs are constantly affected by their inputs as long as the enable signal is asserted. In other words, when they are enabled, their content changes immediately according to their inputs. D-latch and it‘s waveforms are shown in Fig.7&8. Fig.7 D Latch Fig.8 Input and Output Waveforms The architecture of proposed 16-b CSLA is shown in Fig. 8. It has different five groups of different bit size RCA and D-Latch. Instead of using two separate adders in the regular CSLA, in this method only one adder is used. Each of the two additions is performed in one clock cycle. This is 16- bit adder in which least significant bit (LSB) adder is ripple carry adder, which is 2 bit wide. The upper half of the adder i.e., most significant part is 14-bit wide which works according to the clock. Whenever clock goes high addition for carry input one is performed. When clock goes low then carry input is assumed as zero and sum is stored in adder itself. From the Fig.9 it can understand that latch is used to store the sum and carry for Cin=1 and cin=0.Carry out from the previous stage i.e., least significant bit adder is used as control signal for multiplexer to select final output carry and sum of the 16-bit adder. If the actual carry input is one, then computed sum and carry latch is accessed and for carry input zero MSB adder is accessed. Cout is the output carry.](https://image.slidesharecdn.com/fpga-implementation-of-high-speed-architecture-of-csla-using-d-latches-150912102531-lva1-app6892/75/FPGA-Implementation-of-High-Speed-Architecture-of-CSLA-using-D-Latches-7-2048.jpg)
![International Journal of Modern Trends in Engineering and Research (IJMTER) Volume 01, Issue 06, [December - 2014] e-ISSN: 2349-9745, p-ISSN: 2393-8161 @IJMTER-2014, All rights Reserved 8 Fig.9 Modified CSLA Using D Latch The group 2 performed the two bit additions which are a2 with b2 and a3 with b3. This is done by two full adder (FA) named FA2 and FA3 respectively. The third input to the full adder FA2 is the clock instead of the carry and the third input to the full adder FA3 is the carry output from FA2. The group 2 structure has five D-Latches in which four are used for store the sum2 and sum3 from FA2 and FA3 respectively and the last one is used to store carry. Multiplexer is used for selecting the actual sum and carry according to the carry is coming from the previous stage. The 6:3 multiplexer is the combination of 2:1 multiplexer. When the clock is low a2 and b2 are added with carry is equal to zero. Because of low clock, the first D-Latch is not enabled. The second D-Latch store the sum wit cin =0 by using inverted clock enable. When the clock is high, the addition is performed with carry is equal to one. The other D-Latches enabled and store the sum and carry for carry is equal to one. According to the value of c1 whether it is 0 or 1, the multiplexer selected the actual sum and carry. VII. FPGA IMPLEMENTATION RESULTS This work has been developed using VHDL. It was simulated and synthesized using Xilinx 13.2. This design was implemented Spartan 3E kit. Fig. 10(a), 10(b), 10(c), 10(d), 10(e) show the simulation results of regular 16-bit Linear CSLA, regular 16-bit SQRT CSLA, modified 16-bit Linear CSLA, modified 16-bit SQRT CSLA and 16-bit Modified CSLA using D-latch respectively. It is clear that the area of the 16-bit proposed modified SQRT CSLA is reduced when compared with the area of other CSLAs. The Modified CSLA with D-Latches is going to increase the speed compare to all previous works. Fig 10(a) 16 bit Regular Linear CSLA](https://image.slidesharecdn.com/fpga-implementation-of-high-speed-architecture-of-csla-using-d-latches-150912102531-lva1-app6892/75/FPGA-Implementation-of-High-Speed-Architecture-of-CSLA-using-D-Latches-8-2048.jpg)
![International Journal of Modern Trends in Engineering and Research (IJMTER) Volume 01, Issue 06, [December - 2014] e-ISSN: 2349-9745, p-ISSN: 2393-8161 @IJMTER-2014, All rights Reserved 9 Fig 10(b) 16 bit Regular sqrt CSLA Fig 10(c) 16 bit Modified Linear CSLA Fig 10(d) 16 bit Modified Sqrt CSLA](https://image.slidesharecdn.com/fpga-implementation-of-high-speed-architecture-of-csla-using-d-latches-150912102531-lva1-app6892/75/FPGA-Implementation-of-High-Speed-Architecture-of-CSLA-using-D-Latches-9-2048.jpg)
![International Journal of Modern Trends in Engineering and Research (IJMTER) Volume 01, Issue 06, [December - 2014] e-ISSN: 2349-9745, p-ISSN: 2393-8161 @IJMTER-2014, All rights Reserved 10 Fig 10(e) 16 bit Modified CSLA using D-Latch VIII. CONCLUSION This project presented a simple approach to reduce the delay of CSLA architecture. The previous work Modified CSLA is used to reduce the area. The reduced number of gates of this work offers the great advantage in the reduction of area. The area (gate count) of the Modified SQRT CSLA is significantly reduced when compared with Regular Linear. The delay is slightly increased than the previous one. Our proposed project Modified CSLA with D-Latches is increases the speed compare to all previous works. Hence Modified CSLA with D-Latch considered as a high speed adder. REFERENCES [1] B. Ramkumar, H.M. Kittur, and P. M. Kannan, “ASIC implementation of modified faster carry save adder,” Eur. J. Sci. Res., vol. 42, no. 1,pp.53–58, 2010. [2] Y. Kim and L.-S. Kim, “64-bit carry-select adder with reduced area,”Electron. Lett. vol. 37, no. 10, pp. 614–615, May 2001. [3] J. M. Rabaey, Digtal Integrated Circuits—A Design Perspective.Upper Saddle River, NJ: Prentice-Hall, 2001 [4] Y. He, C. H. Chang, and J. Gu, “An area efficient 64-bit square Root carry-select adder for low power applications,” in Proc. IEEE Int.Symp.Circuits Syst., vol. 4, pp. 4082–4085, 2005. [5] Cadence, “Encounter user guide,” Version 6.2.4, March 2008. [6] Ramkumar, B. and Harish M Kittur, “Low Power and Area Efficient Carry Select Adder”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, pp.1-5, 2012. [7] He, Y. Chang, C. H. and Gu, J. “An Area Efficient 64-Bit Square Root Carry-Select Adder for Low Power Applications,” in Proc. IEEE Int.Symp. Circuits Syst., Vol.4, pp. 4082–4085, 2005. [8] Padma Devi, Ashima Girdher and Balwinder Singh “Improved Carry Select Adder with Reduced Area and Low Power Consumption,” International Journal of Computer Applications, Vol.3, No.4, pp. 14-18, 1998. [9] Akhilesh Tyagi, “A Reduced-Area Scheme for Carry-Select Adders,”IEEE Transactions on Computers, Vol.42, No.10, pp.1163-1170, 1993. [10] Edison A.J and C.S.Manikanda babu “An Efficient CSLA Architecture for VLSI Hardware Implementation” International Journal for Mechanical and Industrial Engineering, Vol. 2. Issue 5, 2012.](https://image.slidesharecdn.com/fpga-implementation-of-high-speed-architecture-of-csla-using-d-latches-150912102531-lva1-app6892/75/FPGA-Implementation-of-High-Speed-Architecture-of-CSLA-using-D-Latches-10-2048.jpg)
![International Journal of Modern Trends in Engineering and Research (IJMTER) Volume 01, Issue 06, [December - 2014] e-ISSN: 2349-9745, p-ISSN: 2393-8161 @IJMTER-2014, All rights Reserved 11 [11] P.Sreenivasulu,. K.Srinivasa Rao, Malla Reddy, and A.Vinay Babu “Energy and Area efficient Carry Select Adder on a reconfigurable Hardware” International Journal of Engineering Research and Applications, Vol. 2, Issue 2, pp.436- 440, march 2012. [12] Sarabdeep Singh and Dilip Kumar, “Design of Area and Power efficient Modified Carry Select Adder” International Journal of Computer Applications (0975 – 8887) Volume 33– No.3, November 2011. [13] M.D. Ercegovac and T. Lang, “Digital Arithmetic.” San Francisco: Morgan Daufmann, ISBN 1-55860-798-6, 2004. [14] Israel Koren, “Computer Arithmetic Algorithms.” Pub A K Peters,ISBN 1-56881-160-8, 2002.](https://image.slidesharecdn.com/fpga-implementation-of-high-speed-architecture-of-csla-using-d-latches-150912102531-lva1-app6892/75/FPGA-Implementation-of-High-Speed-Architecture-of-CSLA-using-D-Latches-11-2048.jpg)
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FPGA Implementation of High Speed Architecture of CSLA using D-Latches
This document discusses the FPGA implementation of a modified Carry Select Adder (CSLA) utilizing D-latches to improve area efficiency and speed. It compares the traditional CSLA architecture with the modified version that incorporates a Binary to Excess-1 Converter (BEC) and explores methodologies for area evaluation and performance analysis. The proposed architecture demonstrates significant area savings and efficient addition operations by utilizing fewer logic gates and optimizing the carry propagation mechanism.
FPGA Implementation of High Speed Architecture of CSLA using D-Latches
- 1. Scientific Journal ImpactFactor (SJIF): 1.711 International Journal of Modern Trends in Engineering and Research www.ijmter.com @IJMTER-2014, All rights Reserved 1 e-ISSN: 2349-9745 p-ISSN: 2393-8161 FPGA Implementation of High Speed Architecture of CSLA using D-Latches P.Sajid Khan1 , MD.Shamshad begum2 1 (M.tech_VLSI/SD), 2 M.Tech Assistant.Professor Dept.of E.C.E 1,2 ECE, Nimra college of Engineering and technology Abstract— Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing processors to perform fast arithmetic functions. The CSLA is used in many systems to overcome the problem of carry propagation delay by independently generating multiple carries and then select a carry to generate the sum. But the CSLA is not area efficient because it uses multiple pairs of Ripple Carry Adders (RCA). Due to the rapidly growing mobile industry not only the faster arithmetic unit but also less area and low power arithmetic units are needed. The modified CSLA architecture has developed using Binary to Excess-1 converter (BEC). This paper proposes an efficient method which replaces the BEC using D latch. Designs were developed using structural VHDL and synthesized in Xilinx 13.2 with reference to FPGA device XC3S500E. Keywords: Field Programmable Gate Array (FPGA), D-Latch, Area efficient, Carry Select Adder (CSLA), Square-root CSLA (SQRT CSLA). I. INTRODUCTION Design of area efficient high speed data path logic systems are one of the most essential areas of research in VLSI. In digital adders, the speed of addition is controlled by the time required to propagate a carry through the adder. The sum for each bit position in an elementary adder is generated sequentially only after the previous bit position was summed and a carry propagated into the next position. Bedriji proposed [1] that the problem of carry propagation delay is overcome by independently generating multiple radix carries and using this carries to select between simultaneously generated sums. Akhilash Tyagi introduced a scheme to generate carry bits with block carry in 1 from the carries of a block with block carry in 0 [4]. Chang and Hsiao proposed [3] that instead of using dual Ripple Carry Adder a Carry Select Adder scheme using an add one circuit to replace one RCA. Youngioon Kim and Lee Sup Kim introduced a multiplexer based add one circuit was proposed to reduce the area with negligible speed penalty. Yajuan He et al proposed an area efficient Square-root CSLA (SQRT CSLA) scheme based on a new first zero detection logic [9]. Ramkumar et al proposed a Binary to Excess-1 Converter (BEC) method to reduce the maximum delay of carry propagation in final stage of carry save adder [2]. Ramkumar and Harish proposed [8] BEC technique, which is a simple and efficient gate level modification to significantly reduce the area of SQRT CSLA. Padma Devi et al proposed [10] modified CSLA designed in different stages which reduces the area. CSLA is used in many computational systems to relieve the problem of carry propagation delay by independently generating multiple carries and then select a carry to generate the sum [1].However, the CSLA is not area efficient because it uses multiple pairs of RCA to generate partial sum and carry by considering carry in 0 and carry in 1, then the final sum and carry are selected by the multiplexers (Mux).The basic idea of this work is to use BEC instead of RCA with carry in 1 in the regular CSLA to achieve lower area [2], [3] and [4]. The main benefit of BEC
- 2. International Journal ofModern Trends in Engineering and Research (IJMTER) Volume 01, Issue 06, [December - 2014] e-ISSN: 2349-9745, p-ISSN: 2393-8161 @IJMTER-2014, All rights Reserved 2 comes from the lesser number of logic gates than the n-bit Full Adder (FA). The details of BEC are discussed in section III. Section II also deals with the area evaluation methodology of the basic adder blocks and presents the detailed structure and the function of the BEC. The CSLA has been chosen for comparison with the proposed design as it has a lower area [5], [6]. The area evaluation methodology of the regular Linear CSLA and modified Linear CSLA are presented in section IV. The area evaluation methodology of the regular SQRT CSLA and modified SQRT CSLA are presented in section V. The FPGA implementation details and results are analyzed in section VI. Finally this work is concluded in section VII. II. AREA EVALUATION METHODOLOGY OF THE BASIC ADDER BLOCKS An XOR gate is shown in Fig. 1, which is implemented by using AND, OR and Inverter (NOT). The gates between the dotted lines are performing the operations in parallel. The area evaluation methodology considers all gates to be made up of AND, OR and Inverter (AOI), each having are The area evaluation is done by counting the total gates required for each logic block. Based on the CSLA blocks of 2:1 Mux, Half Adder (Hevaluated and listed in Table I). Fig1. Area evaluation of an XoR gate CSLA AREA COUNTXOR 5 2:1 MUX 4 HA 6 FA 13 Table 1: Area count of the Basic Blocks of CSLA III. BINARY TO EXCESS-1 CONVERTER (BEC) The main idea of this work is to use BEC with carry in=1 in order to reduce the area of t CSLA as well as regular SQRT CSLA. To RCA, an n+1-bit BEC is required. A structure of 3-bit BEC are shown in Fig. 2 and Table II, Boolean expressions for 3-bit BEC is shown functional symbols ~ NOT, & AND, ^ XOR) X0 = ~ B0 (1) X1 = B0 ^ B1 (2) X2 = B2 ^ (B0 & B1) (3)
- 3. International Journal ofModern Trends in Engineering and Research (IJMTER) Volume 01, Issue 06, [December - 2014] e-ISSN: 2349-9745, p-ISSN: 2393-8161 @IJMTER-2014, All rights Reserved 3 Fig2: 3 –bit BEC Table 2: Functional table of 3 bit BEC IV. AREA EVALUATION METHODOLOGY OF REGULAR 16-BIT LINEAR AS WELL AS SQRT CSLA The structure of the 16-bit regular Linear CSLA is shown in Fig. 3. It has 4 groups of same size CA. Each group contains dual RCA and Mux. It accomplishes the addition by adding small portions of bits (each of equal size) and wait for the carry to complete the calculation. Both sum and carry are calculated for both possible solutions. The Linear carry select adder is constructed by chaining a number of equal length adder stages. Here the equal size of inputs is given to each block of the adder. The steps leading to the evaluations are given here. In the regular Linear CSLA, the group2 has two sets of 4-bit RCA. The selection input of 10:5 Mux is c3.If the c3=0, the mux select first RCA output otherwise it select second RCA output. The output of group2 is Sum [7:4] and carryout, c7.Then the area count of group2 is determined as follows Gate count = 117 (FA+HA+MUX) FA = 91 (7 * 13) HA = 6 (1 * 6) Mux = 20 (5 * 4) Similarly the estimated area of the other groups in the regular Linear CSLA are evaluated and listed in Table III Fig3: 16 bit Regular linear CSLA GROUP AREA B[2:0] X[2:0] 000 001 001 010 010 011 011 100 100 101 101 110 110 111 111 000
- 4. International Journal ofModern Trends in Engineering and Research (IJMTER) Volume 01, Issue 06, [December - 2014] e-ISSN: 2349-9745, p-ISSN: 2393-8161 @IJMTER-2014, All rights Reserved 4 GROUP1 52 GROUP2 117 GROUP3 117 GROUP4 117 Table 3: Area count of the 16-bit regular linear CSLA groups The structure of the 16-bit regular SQRT CSLA is Shown in Fig. 4. It has 5 groups of different size RCA. Each group contains dual RCA and Mux. The linear carry select adder has two disadvantages there are high area usage and high time delay. These disadvantages of linear carry select adder can be rectified by SQRT CSLA. It is an improved one of linear CSLA. The time delay of the linear adder can decrease by having one more input into each set of adders than in the previous set. This is called a Square Root Carry Select Adder. Square Root carry select adder is constructed by equalizing the delay through two carry chains and the block-multiplexer signal from previous stage. The steps leading to the evaluations are given here. In the regular SQRT CSLA, the group2 has two sets of 2- bit RCA. The selection input of 3:2 Mux is c1. If the c1 = 0, the Mux select first RCA output otherwise it select second RCA output. The output of group2 are Sum [3:2] and carryout, c3. Then the area count of group2 is determined as follows: Gate count = 57 (FA + HA + Mux) FA = 39 (3 * 13) HA = 6 (1 * 6) Mux = 12 (3 * 4) Similarly the estimated area of the other groups in the regular SQRT CSLA are evaluated and listed in Table IV. GROUP AREA COUNT GROUP1 26 GROUP2 57 GROUP3 87 GROUP4 117 GROUP5 147 Table 4: Area count of the 16-bit regular sqrt CSLA groups
- 5. International Journal ofModern Trends in Engineering and Research (IJMTER) Volume 01, Issue 06, [December - 2014] e-ISSN: 2349-9745, p-ISSN: 2393-8161 @IJMTER-2014, All rights Reserved 5 V. AREA EVALUATION METHODOLOGY OF MODIFIED 16-BIT LINEAR AS WELL AS SQRT CSLA The structure of the proposed 16-bit Linear and SQRT CSLA using BEC for RCA with carry in = 1 to optimize the area is shown in Fig. 5 and Fig. 6 respectively. The 16-bit modified Linear CSLA has 4 groups of same size RCA and BEC. Each group contains one RCA, one BEC and Mux. In the modified Linear CSLA, the group2 has one 4-bit RCA which has 3 FA and 1 HA for carry in = 0. Instead of another 4-bit RCA with carry in = 1 a 5-bit BEC is used which adds one to the output from 4-bit RCA. The selection input of 10:5 Mux is c3. If the c3 = 0, the Mux select RCA output otherwise it select BEC output. The output of group2 are Sum [7:4] and carryout, c7. Then the area count of group2 is determined as follows: Gate count = 89 (FA + HA + Mux + BEC) FA = 39 (3 * 13) HA = 6 (1 * 6) Mux = 20 (5 * 4) NOT = 1 AND = 3 (3 * 1) XOR = 20 (4 * 5) BEC (5-BIT) = NOT + AND + XOR = 24 Similarly the estimated area of the other groups in the modified Linear CSLA are evaluated and listed in Table V.
- 6. International Journal ofModern Trends in Engineering and Research (IJMTER) Volume 01, Issue 06, [December - 2014] e-ISSN: 2349-9745, p-ISSN: 2393-8161 @IJMTER-2014, All rights Reserved 6 Table 5: Area count of the 16-bit modified linear CSLA groups The structure of the 16-bit modified SQRT CSLA is shown in Fig. 6. It has 5 groups of different size RCA and BEC. Each group contains one RCA, one BEC and MUX. In the modified SQRT CSLA, the group2 has one 2-bit RCA which has 1 FA and 1 HA for carry in = 0. Instead of another 2-bit RCA with carry in = 1 a 3-bit BEC is used which adds one to the output from 2-bit RCA. The selection input of 6:3 Mux is c3. If the c3 = 0, the Mux select RCA output otherwise it select BEC output. The output of group2 are Sum [3:2] and carryout,c3. Then the area count of group2 is determined as follows: Gate count = 43 (FA + HA + Mux + BEC) FA = 13 (1 * 13) HA = 6 (1 * 6) Mux = 12 (3 * 4) NOT = 1 AND = 1 XOR = 10 (2 * 5) BEC (3-BIT) = NOT + AND + XOR = 12 Similarly the estimated area of the other groups in the modified SQRT CSLA are evaluated and listed in Table VI. Table 6: Area count of the 16-bit modified sqrt CSLA groups
- 7. International Journal ofModern Trends in Engineering and Research (IJMTER) Volume 01, Issue 06, [December - 2014] e-ISSN: 2349-9745, p-ISSN: 2393-8161 @IJMTER-2014, All rights Reserved 7 Comparing Tables III and IV with Tables V and VI, it is clear that the proposed modified Linear as well as SQRT CSLA save 84 gate and 97 gate areas than the regular Linear CSLA and regular SQRT CSLA respectively. VI. MODIFIED 16-BIT CSLA USING D-LATCH This method replaces the BEC add one circuit by D-latch with enable signal. Latches are used to store one bit information. Their outputs are constantly affected by their inputs as long as the enable signal is asserted. In other words, when they are enabled, their content changes immediately according to their inputs. D-latch and it‘s waveforms are shown in Fig.7&8. Fig.7 D Latch Fig.8 Input and Output Waveforms The architecture of proposed 16-b CSLA is shown in Fig. 8. It has different five groups of different bit size RCA and D-Latch. Instead of using two separate adders in the regular CSLA, in this method only one adder is used. Each of the two additions is performed in one clock cycle. This is 16- bit adder in which least significant bit (LSB) adder is ripple carry adder, which is 2 bit wide. The upper half of the adder i.e., most significant part is 14-bit wide which works according to the clock. Whenever clock goes high addition for carry input one is performed. When clock goes low then carry input is assumed as zero and sum is stored in adder itself. From the Fig.9 it can understand that latch is used to store the sum and carry for Cin=1 and cin=0.Carry out from the previous stage i.e., least significant bit adder is used as control signal for multiplexer to select final output carry and sum of the 16-bit adder. If the actual carry input is one, then computed sum and carry latch is accessed and for carry input zero MSB adder is accessed. Cout is the output carry.
- 8. International Journal ofModern Trends in Engineering and Research (IJMTER) Volume 01, Issue 06, [December - 2014] e-ISSN: 2349-9745, p-ISSN: 2393-8161 @IJMTER-2014, All rights Reserved 8 Fig.9 Modified CSLA Using D Latch The group 2 performed the two bit additions which are a2 with b2 and a3 with b3. This is done by two full adder (FA) named FA2 and FA3 respectively. The third input to the full adder FA2 is the clock instead of the carry and the third input to the full adder FA3 is the carry output from FA2. The group 2 structure has five D-Latches in which four are used for store the sum2 and sum3 from FA2 and FA3 respectively and the last one is used to store carry. Multiplexer is used for selecting the actual sum and carry according to the carry is coming from the previous stage. The 6:3 multiplexer is the combination of 2:1 multiplexer. When the clock is low a2 and b2 are added with carry is equal to zero. Because of low clock, the first D-Latch is not enabled. The second D-Latch store the sum wit cin =0 by using inverted clock enable. When the clock is high, the addition is performed with carry is equal to one. The other D-Latches enabled and store the sum and carry for carry is equal to one. According to the value of c1 whether it is 0 or 1, the multiplexer selected the actual sum and carry. VII. FPGA IMPLEMENTATION RESULTS This work has been developed using VHDL. It was simulated and synthesized using Xilinx 13.2. This design was implemented Spartan 3E kit. Fig. 10(a), 10(b), 10(c), 10(d), 10(e) show the simulation results of regular 16-bit Linear CSLA, regular 16-bit SQRT CSLA, modified 16-bit Linear CSLA, modified 16-bit SQRT CSLA and 16-bit Modified CSLA using D-latch respectively. It is clear that the area of the 16-bit proposed modified SQRT CSLA is reduced when compared with the area of other CSLAs. The Modified CSLA with D-Latches is going to increase the speed compare to all previous works. Fig 10(a) 16 bit Regular Linear CSLA
- 9. International Journal ofModern Trends in Engineering and Research (IJMTER) Volume 01, Issue 06, [December - 2014] e-ISSN: 2349-9745, p-ISSN: 2393-8161 @IJMTER-2014, All rights Reserved 9 Fig 10(b) 16 bit Regular sqrt CSLA Fig 10(c) 16 bit Modified Linear CSLA Fig 10(d) 16 bit Modified Sqrt CSLA
- 10. International Journal ofModern Trends in Engineering and Research (IJMTER) Volume 01, Issue 06, [December - 2014] e-ISSN: 2349-9745, p-ISSN: 2393-8161 @IJMTER-2014, All rights Reserved 10 Fig 10(e) 16 bit Modified CSLA using D-Latch VIII. CONCLUSION This project presented a simple approach to reduce the delay of CSLA architecture. The previous work Modified CSLA is used to reduce the area. The reduced number of gates of this work offers the great advantage in the reduction of area. The area (gate count) of the Modified SQRT CSLA is significantly reduced when compared with Regular Linear. The delay is slightly increased than the previous one. Our proposed project Modified CSLA with D-Latches is increases the speed compare to all previous works. Hence Modified CSLA with D-Latch considered as a high speed adder. REFERENCES [1] B. Ramkumar, H.M. Kittur, and P. M. Kannan, “ASIC implementation of modified faster carry save adder,” Eur. J. Sci. Res., vol. 42, no. 1,pp.53–58, 2010. [2] Y. Kim and L.-S. Kim, “64-bit carry-select adder with reduced area,”Electron. Lett. vol. 37, no. 10, pp. 614–615, May 2001. [3] J. M. Rabaey, Digtal Integrated Circuits—A Design Perspective.Upper Saddle River, NJ: Prentice-Hall, 2001 [4] Y. He, C. H. Chang, and J. Gu, “An area efficient 64-bit square Root carry-select adder for low power applications,” in Proc. IEEE Int.Symp.Circuits Syst., vol. 4, pp. 4082–4085, 2005. [5] Cadence, “Encounter user guide,” Version 6.2.4, March 2008. [6] Ramkumar, B. and Harish M Kittur, “Low Power and Area Efficient Carry Select Adder”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, pp.1-5, 2012. [7] He, Y. Chang, C. H. and Gu, J. “An Area Efficient 64-Bit Square Root Carry-Select Adder for Low Power Applications,” in Proc. IEEE Int.Symp. Circuits Syst., Vol.4, pp. 4082–4085, 2005. [8] Padma Devi, Ashima Girdher and Balwinder Singh “Improved Carry Select Adder with Reduced Area and Low Power Consumption,” International Journal of Computer Applications, Vol.3, No.4, pp. 14-18, 1998. [9] Akhilesh Tyagi, “A Reduced-Area Scheme for Carry-Select Adders,”IEEE Transactions on Computers, Vol.42, No.10, pp.1163-1170, 1993. [10] Edison A.J and C.S.Manikanda babu “An Efficient CSLA Architecture for VLSI Hardware Implementation” International Journal for Mechanical and Industrial Engineering, Vol. 2. Issue 5, 2012.
- 11. International Journal ofModern Trends in Engineering and Research (IJMTER) Volume 01, Issue 06, [December - 2014] e-ISSN: 2349-9745, p-ISSN: 2393-8161 @IJMTER-2014, All rights Reserved 11 [11] P.Sreenivasulu,. K.Srinivasa Rao, Malla Reddy, and A.Vinay Babu “Energy and Area efficient Carry Select Adder on a reconfigurable Hardware” International Journal of Engineering Research and Applications, Vol. 2, Issue 2, pp.436- 440, march 2012. [12] Sarabdeep Singh and Dilip Kumar, “Design of Area and Power efficient Modified Carry Select Adder” International Journal of Computer Applications (0975 – 8887) Volume 33– No.3, November 2011. [13] M.D. Ercegovac and T. Lang, “Digital Arithmetic.” San Francisco: Morgan Daufmann, ISBN 1-55860-798-6, 2004. [14] Israel Koren, “Computer Arithmetic Algorithms.” Pub A K Peters,ISBN 1-56881-160-8, 2002.