System-on-Chip Design

with SystemC

Joachim Gerlach <gerlach@informatik.uni-tuebingen.de>

University of Tübingen
Wilhelm-Schickard-Institut
Department of Computer Engineering
University of
Tübingen Contents
Department of
Computer
Engineering
q Background & Basics
m System-on-Chip Design
Background
& Basics m C/C++ Based System Design

SystemC 1.0 m The SystemC Approach

Design m SystemC Licensing Model

Example A
m Open SystemC Community
Design
Example B
q Introduction to SystemC 1.0
Design
Activities m Modules & Hierarchie

Tool m Processes
Support
m Ports & Signals
SystemC 1.1
m Data Types & Fixed Point Data Types

Joachim q Design Example A

Gerlach
m Simple 2-Process Scenario

Joachim Gerlach System-on-Chip Design with SystemC 1

University of
Tübingen Contents
Department of
Computer
Engineering

q Design Example B
Background m JPEG Compression / Decompression Stream
& Basics

SystemC 1.0 q Design Activities

Design m Modeling
Example A
m Simulation
Design
Example B m Debugging

Design
Activities q Tool Support
Tool m Synopsys: SystemC Compiler
Support
m CoWare: N2C
SystemC 1.1
m C-Level Design: System Compiler
m Frontier Design: AxRT Builder
Joachim
Gerlach
q Outlook to SystemC 1.1

Joachim Gerlach System-on-Chip Design with SystemC 2

TM
SYSTEMC

Background & Basics

University of Tübingen
Wilhelm-Schickard-Institut
Department of Computer Engineering
University of
Tübingen Productivity Gap
Department of
Computer
Engineering
complexity
[gates]
Background 1G
& Basics 256M
memory
100M 64M higher
SystemC 1.0 processors abstraction
16M
gates / chip level
Design 10M 4M
Example A Pentium II IP re-use
1M Pentium (0,35 µm)
1M (0,8 µm)
Design 256K 486DX
Example B hardware
100K 64K 386DX
productivity software
Design 16K co-design
Activities 8088 gap
10K 4K
1K design
Tool 8080 automation
8008 (source: ICE)
Support 1K
1970 1980 1990 2000
SystemC 1.1 gates / day

time
Wolfgang 1980 1990 2000
Rosenstiel (source: MEDEA Design Automation Roadmap 1999)

Joachim Gerlach System-on-Chip Design with SystemC 4

University of
Tübingen System Level Design
Department of
Computer
Engineering
q System-on-Chips (SoC) designs
q SoC designs contain
Background
& Basics
m Multiple design domains: hardware, software, analog, ...
SystemC 1.0
m Multiple source components: DSPs, ASICs, IP-Cores, ...
Design
Example A m Hard constraints: realtime, low power, ...
Design
Example B

Design
Activities

Tool
Support

SystemC 1.1

Wolfgang
Rosenstiel

Joachim Gerlach System-on-Chip Design with SystemC 5

University of
Tübingen System Level Design Flow
Department of
Computer
Engineering
specification

Background functional architectural

co-design
& Basics validation validation

SystemC 1.0
algorithmic architectural
Design
models models
Example A

Design software hw/sw hardware

Example B co-simulation
implementation implementation
co-verification
Design
Activities

hardware architecture
software architecture

Tool
device memory
Support driver map
SystemC 1.1 processor &
RTOS peripherals

Wolfgang application
Rosenstiel user specific
software co-processor

Joachim Gerlach System-on-Chip Design with SystemC 6

University of
Tübingen Benefits of a C/C++ Based Design Flow
Department of
Computer
Engineering
q Productivity aspect
m Specification between architect and implementer is executable
Background
& Basics
m High speed and high level simulation and prototyping
SystemC 1.0
m Refinement, no translation into hardware (no “semantic gap”)
Design
Example A q System level aspect
Design
Example B m Tomorrow’s systems designers will be designing
Design
mostly C/C++
software and less hardware !
Activities

Tool
m
System SoC
Co-design, co-simulation, co-verification, co-debugging, ...
Support

SystemC 1.1
q Re-use aspect
Architect
Design Marketing
& Sales
m OptimumC/C++
re-use support by object-oriented techniques
HDL
Wolfgang
m Efficient testbench re-use
Rosenstiel
q Software
Especially C/C++ is widespread Hardware
and commonly used !
Designer Designer

Joachim Gerlach System-on-Chip Design with SystemC 7

University of
Tübingen Drawbacks of a C/C++ Based Design Flow
Department of
Computer
Engineering
q C/C++ is not created to design hardware !
q C/C++ does not support
Background
& Basics
m Hardware style communication
SystemC 1.0
l Signals, protocols
Design
Example A
m Notion of time
Design
l Clocks, time sequenced operations
Example B m Concurrency
Design l Hardware is inherently concurrent, operates in parallel
Activities

Tool
m Reactivity
Support l Hardware is inherently reactive, responds to stimuli,
SystemC 1.1 interacts with its environment (→ requires handling of exceptions)
m Hardware data types
Wolfgang l Bit type, bit-vector type, multi-valued logic types,
Rosenstiel signed and unsigned integer types, fixed-point types

Joachim Gerlach System-on-Chip Design with SystemC 8

University of
Tübingen How to Get “Synthesizable C/C++” ?
Department of
Computer
Engineering

q Step-1: C
Background
& Basics synthesizable
restriction to subset of C
SystemC 1.0
synthesizable subset
Design
Example A
synthesizable
q Step-2: C++ subset of C++
Design
Example B extension by
Design hardware-related hardware type
Activities
components communication hardware
Tool data types
Support m new language constructs
synthesizable
SystemC 1.1
(HardwareC, C*) notion subset
of time reactivity
m library based approach
concurrency
Wolfgang (SystemC, Cynlib)
Rosenstiel

q Step-1 and step-2 can be swapped !

Joachim Gerlach System-on-Chip Design with SystemC 9

University of
Tübingen Why SystemC for System Design ?
Department of
Computer
Engineering
q The Gap

Background m Tomorrow’s systems designers will be designing

& Basics mostly software and little hardware
SystemC 1.0 m A software language is not capable of describing
Design concurrency, clocks, hardware data types, reactivity
Example A

Design
Example B q Requirements
Design
Activities m Allow hardware/software co-design and co-verification
Tool m Fast simulation for validation and optimization
Support
m Smooth path to hardware and software
SystemC 1.1
m Support of design and architectural re-use
Joachim
Gerlach

Joachim Gerlach System-on-Chip Design with SystemC 10

University of
Tübingen What is SystemC ?
Department of
Computer
Engineering
q A library of C++ classes
m Processes (for concurrency)
Background
& Basics m Clocks (for time)

SystemC 1.0 m Modules, ports, signals (for hierarchy)

Design m Waiting, watching (for reactivity)

Example A
m Hardware data types
Design
Example B
q A modeling style
Design
Activities m ... for modeling systems consisting of multiple
Tool design domains, abstraction levels, architectural
Support components, real-life constraints
SystemC 1.1

q A light-weight simulation kernel

Joachim m ... for high-speed cycle-accurate simulation
Gerlach

Joachim Gerlach System-on-Chip Design with SystemC 11

University of
Tübingen How Does it Work ?
Department of
Computer
Engineering

System
Background C/C++ Software
& Basics
C/C++ Testbench Component
SystemC 1.0
DSP
Design IP-Core
Example A
Modeling C/C++ Hardware ASIC
Design Constructs Component
Example B Interface
Design
Activities

Tool SystemC
Support Standard
SystemC 1.1
C++ Compiler

Joachim
Gerlach
Executable = Simulator

Joachim Gerlach System-on-Chip Design with SystemC 12

University of
Tübingen Benefits of a SystemC-Based Design Flow
Department of
Computer
Engineering
q Classical HDL based design methodology

Background
& Basics

SystemC 1.0
system 4. hand over
Design architect
Example A specification
C/C++ document
Design
Example B

Design HDL
Activities
1. conceptualize 6. (re)implement in HDL
Tool
2. simulate in C/C++ 7. (re)validate HDL
7. implementation
Support 3. write specification
SystemC 1.1 3. document 8. synthesize from HDL

hardware
Wolfgang designer
Rosenstiel

Joachim Gerlach System-on-Chip Design with SystemC 13

University of
Tübingen Benefits of a SystemC-Based Design Flow
Department of
Computer
Engineering
q C/C++ based design methodology

Background C/C++
& Basics

SystemC 1.0
1. conceptualize
Design 2. simulate in C/C++
Example A
3. write specification document
Design
Example B
system 4. hand over
Design architect • executable specification hardware
Activities • testbenches designer
Tool • written specification C/C++
Support
5. understand specification
SystemC 1.1
6. refine in C/C++
7. validate re-using testbenches
Wolfgang
Rosenstiel 8. synthesize from C/C++

Joachim Gerlach System-on-Chip Design with SystemC 14

University of
Tübingen The SystemC Approach
Department of
Computer
Engineering
q The requirements...
m Fast system modeling containing multiple source components
Background
& Basics
m Model once for multiple abstraction level, multiple users,
SystemC 1.0 multiple purposes
Design
Example A
q The problem...
Design
Example B m No common format for describing components
Design
Activities
q The approach...
Tool
Support m Promote a standard C/C++ based modeling platform
SystemC 1.1
... to model and exchange system level components and IP
... to build interoperable tools infrastructure
Wolfgang
Rosenstiel

Joachim Gerlach System-on-Chip Design with SystemC 15

University of
Tübingen The SystemC Approach
Department of
Computer
Engineering
q Why C/C++ based ?
m Specification between architect and implementer is executable
Background
& Basics
m High simulation speed at higher level of abstraction
SystemC 1.0
m Refinement, no translation into HDL (no “semantic gap”)
Design
Example A m Efficient testbench re-use
Design
Example B
C/C++
Design
Activities

Tool System SoC

Support Architect
Design Marketing
& Sales
SystemC 1.1
C/C++
HDL

Wolfgang
Rosenstiel Software Hardware
Designer Designer

Joachim Gerlach System-on-Chip Design with SystemC 16

University of
Tübingen SystemC Modeling Platform
Department of
Computer
Engineering

TM

Background
S Y S T E M C is...
& Basics

SystemC 1.0 ... a methodology for modeling SoC designs consisting of

Design ... DSPs, ASICs, IP-Cores, Interfaces, ...
Example A

Design ... a C++ library extending C/C++ by concurrency, timing,

Example B
... reactivity, communication, signal / data types, ...
Design
Activities

Tool
... a cycle-accurate high-speed simulation
Support

SystemC 1.1

Wolfgang
Rosenstiel

Joachim Gerlach System-on-Chip Design with SystemC 17

University of
Tübingen SystemC Design Methodology
Department of
Computer
Engineering

your standard
C/C++ development DSP
Background
environment ASIC
& Basics
Interface
header files IP-Core
SystemC 1.0 compiler

........
Design libraries
Example A
linker

Design class library debugger

Example B and

....
simulation kernel source files
Design for system and
Activities testbenches
„make“
Tool
Support e
utabl on “
SystemC 1.1 ex ec icati
„ ecif a.out
sp
executable = simulation
Wolfgang
Rosenstiel

Joachim Gerlach System-on-Chip Design with SystemC 18

University of
Tübingen SystemC Key Features
Department of
Computer
Engineering
q Concurrency (Sync. and async. processes)
q Notion of time (Multiple clocks with arbitrary phase relation)
Background
& Basics
q Data types (Bit vectors, arbitrary precision integers, ...)
SystemC 1.0 v1.0: arbitrary precision fixed point data types
Design
Example A q Communication (Signals, channels)
v1.0: advanced communication protocols
Design
Example B
q Reactivity (Watching for events)
Design
Activities q Debug support (Waveform tracing)
Tool
Support q Simulation support
SystemC 1.1 q Support of multiple abstraction levels and iterative refinement
q Support of functional model creation
Wolfgang
Rosenstiel
q ....

Joachim Gerlach System-on-Chip Design with SystemC 19

University of
Tübingen Open Community Licensing
Department of
Computer
Engineering
q How to get SystemC ?

Background
& Basics
Steering Group SystemC v0.9
SystemC 1.0 including:
• Modeling specification
Design
Example A • Source code
(reference implementation)
Design download • Reference manual
Example B

Design
Activities

Tool
Support
www.SystemC.org click-through web-based
license agreement
SystemC 1.1

Wolfgang User
Rosenstiel

Joachim Gerlach System-on-Chip Design with SystemC 20

University of
Tübingen Open SystemC Steering Group
Department of
Computer
Engineering
q ARM
q Cadence
Background
& Basics q CoWare
SystemC 1.0 q Ericsson
Design q Fujitsu Microelectronics
Example A
q Infineon Technologies
Design
Example B q Lucent Technologies
Design
Activities
q Motorola
Tool q NEC
Support
q Sony Corporation
SystemC 1.1
q STMicroelectronics

Wolfgang
q Synopsys
Rosenstiel
q Texas Instruments

Joachim Gerlach System-on-Chip Design with SystemC 21

University of
Tübingen Community Charter Members
Department of
Computer
Engineering Actel Fujitsu Microelectronics Sony Corporation
Alcatel Genedax Stellar Semiconductor
Altera Corporation IKOS Systems STMicroelectronics

Background American Applied Research I-Logix Summit Design

& Basics Aptix Infineon Technologies Sun Microsystems
Arcadia Design Systems Integrated Silicon Systems SynaptiCAD
SystemC 1.0 ARC Cores Intellectual Property Synchronicity
Aristo Technology Internet CAD Synopsys
Design
ARM JTA Research Tensilica
Example A
Billions of Operations Per Second LogicVision Texas Instruments
Design CAE Plus Lucent Technologies TransModeling
Example B Chameleon Systems Magma Design Automation Ultima
Co-Design Automation MIPS Technologies Verplex
Design CoWare Monterey Design Systems Viewlogic
Activities
CSELT Motorola Virtio

Tool Denali Red Hat Virtual Silicon Technologies

Support Ericsson Seva Technologies (Intrinsix) Willamette HDL

Frequency Technology Sican Microelectronics Wind River Systems
SystemC 1.1 Frontier Design Snaketech Xilinx

Wolfgang
Rosenstiel

Joachim Gerlach System-on-Chip Design with SystemC 22

University of
Tübingen Open Community Licensing
Department of
Computer
Engineering
q Community members
m No licensing fees, anybody / any company is free and welcome
Background
& Basics to join the community
SystemC 1.0 m Right and responsability to contribute enhancements
Design
Example A
m Designers can create and share models with other companies,
EDA vendors can build SystemC based tools
Design
Example B
q Steering Group
Design
Activities
m Drives convergence and interoperability
Tool
Support m Ensures open evolution and structured innovation
SystemC 1.1
q Goal:
Wolfgang m Make SystemC a de-facto-standard for system-level design
Rosenstiel
m Provide a foundation to build a market upon

Joachim Gerlach System-on-Chip Design with SystemC 23

University of
Tübingen SystemC
Department of
Computer
Engineering
q Short History of SystemC

Background
& Basics

SystemC 1.0
V0.9 launches V1.0 release
Design Scenery 9/27/1999 3/28/2000
Example A

Design
Example B

Design 1997 DAC Paper fixed point datatypes

Activities

Tool
Support HDL constructs
SystemC 1.1
1997 1998 1999 2000

Wolfgang
Rosenstiel

Joachim Gerlach System-on-Chip Design with SystemC 24

University of
Tübingen SystemC
Department of
Computer
Engineering
q European SystemC Users Group
m Communication platform for SystemC users
Background take a look at:
& Basics
m Information flow between SystemC users und Steering Group
www-ti.informatik.uni-tuebingen.de/~systemc
SystemC 1.0
m Acceleration of SystemC evolution and standardization
Design
Example A m Events:
Design European SystemC™
Example B FDL’2000 Users Group Conference
(with DATE’2001)
Design
Activities
1st European SystemC™ 2nd European SystemC™ 3rd European SystemC™
Tool Users Group Meeting Users Group Meeting Users Group Meeting
Support

SystemC 1.1 SystemC™

Release 1.0

Wolfgang
Rosenstiel 2000 2001
January 31 March 28 June 30 September 4-8 March 12-16
2000 2000 2000 2000 2001

Joachim Gerlach System-on-Chip Design with SystemC 25

TM
SYSTEMC

SystemC 1.0
University of Tübingen
Wilhelm-Schickard-Institut
Department of Computer Engineering
University of
Tübingen Modules
Department of
Computer
Engineering
q Modules are basic building blocks of a SystemC design
q A module contains processes (Õ functionality)
Background and/or sub-modules (Õ hierarchical structure)
& Basics

SystemC 1.0
SC_MODULE( module_name ) {
Design
Example A
// Declaration of module ports
// Declaration of module signals
Design
Example B // Declaration of processes
// Declaration of sub-modules
Design
Activities SC_CTOR( module_name ) { // Module constructor
Tool
// Specification of process type and sensitivity
Support // Sub-module instantiation and port mapping
SystemC 1.1 }
// Initialization of module signals
};
Joachim
Gerlach

Joachim Gerlach System-on-Chip Design with SystemC 27

University of
Tübingen Modules
Department of
Computer
Engineering
q A module correspond to a C++ class
class data members Ö ports
Background
& Basics class member functions Ö processes
class constructor Ö process generation
SystemC 1.0

Design
.....
Example A

Design SC_MODULE( module_name ) {

Example B
.....
Design
Activities
};

Tool
Support struct module_name : sc_module {
SystemC 1.1 .....
};
Joachim
Gerlach

Joachim Gerlach System-on-Chip Design with SystemC 28

University of
Tübingen Ports
Department of
Computer
Engineering
q External interface of a module
q Passing data from and to processes / sub-modules
Background
& Basics q Triggering of actions within the module
SystemC 1.0 q A ports has a mode (direction) and a type
mode: in, out, inout
Design
Example A type: C++ type, SystemC type, user-defined type
Design
Example B // input port declaration
sc_in< type > in_port_name;
Design
Activities // output port declaration
sc_out< type > out_port_name;
Tool
Support // bidirectional port declaration
SystemC 1.1 sc_inout< type > inout_port_name;

q Vector port / port array:

Joachim
Gerlach
sc_out< int > result [32];

Joachim Gerlach System-on-Chip Design with SystemC 29

University of
Tübingen Signals
Department of
Computer
Engineering
q Connects a port of one module to the port of another module
q Local to a module
Background
& Basics q Signal semantics is the same as VHDL and Verilog
deferred assignment semantics
SystemC 1.0
q A signal has a type
Design
Example A type: C++ type, SystemC type, user-defined type
Design
Example B
// signal declaration
sc_signal< type > signal_name;
Design
Activities
q Vector signal / signal array:
Tool
Support sc_signal< double > a[4];
SystemC 1.1

q Internal data storage not by signals but by local variables

Joachim
Gerlach
Local variable types: C++ types, SystemC types, user-defined types

Joachim Gerlach System-on-Chip Design with SystemC 30

University of
Tübingen Ports & Signals
Department of
Computer
Engineering
q Port and Signal Binding
m Ports and signals to be bound need to have the same type
Background
& Basics m A signal connects two ports
SystemC 1.0 m A port is bound to one signal (port-to-signal)
Design or to one sub-module port (port-to-port)
Example A

Design
Example B q Resolution
Design m SystemC supports resolved ports and signals
Activities
m Resolved ports/signals have 4-valued logic type (0,1,Z,X)
Tool
Support m Resolved ports/signals allow multiple drivers

SystemC 1.1 m Resolved vector ports/vector signals

sc_in_rv< n > x; // n bits wide resolved input port

Joachim sc_signal_rv< n> y; // n bits wide resolved signal
Gerlach

Joachim Gerlach System-on-Chip Design with SystemC 31

University of
Tübingen Clocks
Department of
Computer
Engineering
q SystemC provides a special object sc_clock
q Clocks generate timing signals to synchronize events
Background
& Basics q Multiple clocks with arbitrary phase relations are supported
SystemC 1.0
q Clock generation:
Design
Example A sc_clock clock_name (“label”, period, duty_ratio, offset, start_value);

Design
Example B
Example: sc_clock my_clk (“CLK”, 20, 0.5, 5, true);
true
Design
Activities false 5 20

Tool 0 5 15 25 35 45 55
Support
q Clock binding:
SystemC 1.1
Example: my_module.clk( my_clk.signal() );
Joachim
Gerlach

Joachim Gerlach System-on-Chip Design with SystemC 32

University of
Tübingen Data Types
Department of
Computer
Engineering
q SystemC supports
m Native C/C++ types
Background
& Basics m SystemC types

SystemC 1.0 m User-defined types

Design
Example A q SystemC types
Design m 2-value (‘0’, ‘1’) logic / logic vector
Example B
m 4-value (‘0’, ‘1’, ‘Z’, ‘X’) logic / logic vector
Design
Activities m Arbitrary sized integer (signed/unsigned)

Tool m Fixed point types (signed/unsigned, templated/untemplated)

Support

SystemC 1.1

Joachim
Gerlach

Joachim Gerlach System-on-Chip Design with SystemC 33

University of
Tübingen Native C/C++ Data Types
Department of
Computer
Engineering
q Integer types:
m char
Background
& Basics m unsigned char

SystemC 1.0 m short

Design m unsigned short

Example A
m int
Design
Example B m unsigned int

Design m long
Activities
m unsigned long
Tool
Support
q Floating point types
SystemC 1.1
m float
m double
Joachim
Gerlach m long double

Joachim Gerlach System-on-Chip Design with SystemC 34

University of
Tübingen SystemC Data Types
Department of
Computer
Engineering
Type Description

Background sc_bit 2-value single bit

& Basics
sc_logic 4-value single bit
SystemC 1.0
sc_int 1 to 64 bit signed integer
Design
Example A sc_uint 1 to 64 bit unsigned integer
Design sc_bigint arbitrary sized signed integer
Example B
sc_biguint arbitrary sized unsigned integer
Design
Activities sc_bv arbitrary length 2-value vector
Tool sc_lv arbitrary length 4-value vector
Support
sc_fixed templated signed fixed point
SystemC 1.1
sc_ufixed templated unsigned fixed point
sc_fix untemplated signed fixed point
Joachim
Gerlach sc_ufix untemplated unsigned fixed point

Joachim Gerlach System-on-Chip Design with SystemC 35

University of
Tübingen sc_bit / sc_logic
Department of
Computer
Engineering
q 2-value single bit type: sc_bit
m ‘0’=false, ‘1’=true
Background
& Basics
q 4-value single bit type: sc_logic
SystemC 1.0
m ‘0’=false, ‘1’=true, ‘X’=unknown/indeterminate value,
Design ‘Z’=high-impedance/floating value
Example A

Design q Features:
Example B
m Mixed use of operand types sc_bit and sc_logic
Design
Activities m Use of character literals for constant assignments
Tool
Support q sc_bit / sc_logic operators
SystemC 1.1
Bitwise & (and) | (or) ^ (xor) ~ (not)
Assignment = &= |= ^=
Joachim
Gerlach Equality == !=

Joachim Gerlach System-on-Chip Design with SystemC 36

University of
Tübingen sc_int / sc_uint / sc_bigint / sc_biguint
Department of
Computer
Engineering
q Fixed precision integer types
m Signed: tsc_int<n> (n: word length, 1 ≤ n ≤ 64)
m Unsigned: sc_uint<n> (n: word length, 1 ≤ n ≤ 64)
Background
& Basics

SystemC 1.0
q Arbitrary precision integer types
Design
Example A m Signed: tsc_bigint<n> (n: word length, n > 64)
Design m Unsigned: sc_biguint<n> (n: word length, n > 64)
Example B

Design q Features:
Activities
m Mixed use of operand types sc_int, sc_uint, sc_bigint,
Tool sc_biguint and C++ integer types
Support
m Truncation and/or sign extension if required
SystemC 1.1
m 2’s complement representation

Joachim
Gerlach

Joachim Gerlach System-on-Chip Design with SystemC 37

University of
Tübingen sc_int / sc_uint / sc_bigint / sc_biguint
Department of
Computer
Engineering
q sc_int / sc_uint / sc_bigint / sc_biguint operators
Bitwise & | ^ ~ >> <<
Background Arithmetic + - * / %
& Basics
Assignment = += -= *= /= %= &= |= ^=
SystemC 1.0 Equality == !=
Design Relational < <= > >=
Example A
Auto-Ink/Dek ++ --
Design Bit/Part Select [] range()
Example B
Concatenation (,)
Design
Activities

Tool
Support

SystemC 1.1

Joachim
Gerlach

Joachim Gerlach System-on-Chip Design with SystemC 38

University of
Tübingen sc_bv / sc_lv
Department of
Computer
Engineering
q Arbitrary length bit vector: jsc_bv<n> (n: vector length)
q Arbitrary length logic vector: sc_lv<n> (n: vector length)
Background
& Basics
q Features:
SystemC 1.0
m Assignment between sc_bv and sc_lv
Design
Example A m Use of string literals for vector constant assignments

Design m Conversions between sc_bv/sc_lv and SystemC integer types

Example B
m No arithmetic operation available
Design
Activities q sc_bv / sc_lv
Tool Bitwise & | ^ ~ >> <<
Support
Assignment = += -= *= /= %= &= |= ^=
SystemC 1.1 Equality == !=
Bit/Part Select [] range()
Joachim Concatenation (,)
Gerlach
Reduction and_reduction() or_reduction() xor_reduction()
Conversion to_string()

Joachim Gerlach System-on-Chip Design with SystemC 39

University of
Tübingen sc_fixed / sc_ufixed / sc_fix / sc_ufix
Department of
Computer
Engineering
q Fixed point types
m sc_fixed templated
Background
& Basics m sc_ufixed signed
unsigned
SystemC 1.0 m sc_fix
untemplated
Design m sc_ufix
Example A

Design q templated - static arguments (to be known at compile time)

Example B
untemplated - nonstatic arguments (to be configured during runtime)
Design
Activities
q signed - 2’s complement representation
Tool
Support unsigned
SystemC 1.1
q Features:
m Operations performed using arbitrary precision
Joachim
Gerlach m Multiple quantization and overflow modes

Joachim Gerlach System-on-Chip Design with SystemC 40

University of
Tübingen sc_fixed / sc_ufixed / sc_fix / sc_ufix
Department of
Computer
Engineering
q Templated signed fixed point type: sc_fixed
sc_fixed< wl, iwl, q_mode, o_mode, n_bits > var_name (init_val);
Background
& Basics

SystemC 1.0 q Arguments:

Design m wl - total number of bits
Example A
m iwl - number of integer bits
Design
Example B m q_mode - quantization mode (optional)
Design m o_mode - overflow_mode (optional)
Activities
m n_bits - number of bits for overflow mode (optional)
Tool
Support

SystemC 1.1

Joachim
Gerlach

Joachim Gerlach System-on-Chip Design with SystemC 41

University of
Tübingen sc_fixed / sc_ufixed / sc_fix / sc_ufix
Department of
Computer
Engineering
q Example:

Background sc_fixed< 8, 4 > my_var (-1.75);

& Basics

SystemC 1.0
( 1.75 )10 = ( 0001.1100 )2
Design 4
Example A 8
Design
Example B 1’s complement of ( 0001.1100 )2 = ( 1110.0011 )2
Design 2’s complement of ( 0001.1100 )2 = ( 1110.0100 )2
Activities

Tool my_var: sign bit

Support

SystemC 1.1 1 1 1 0 0 1 0 0

integer bits fractional bits

Joachim
Gerlach

Joachim Gerlach System-on-Chip Design with SystemC 42

University of
Tübingen sc_fixed / sc_ufixed / sc_fix / sc_ufix
Department of
Computer
Engineering
q Quantization and overflow modes

Background
& Basics Quantization Mode Overflow Mode

SystemC 1.0 Rounding to plus infinity Saturation

Design Rounding to zero Saturation to zero

Example A
Rounding to minus infinity Symmetrical saturation
Design Convergent rounding Wrap-around
Example B
Truncation Sign-magnitude wrap-around
Design
Activities Truncation to Zero
Tool
Support

SystemC 1.1

Joachim
Gerlach

Joachim Gerlach System-on-Chip Design with SystemC 43

University of
Tübingen User-Defined Data Types
Department of
Computer
Engineering
q User-defined data types can be used for ports and signals
sc_signal< complex > c;
Background
& Basics where class complex {
SystemC 1.0 private:
double re;
Design double im;
Example A
public:
Design complex () {`re=0.0; im=0.0; }
Example B
complex (double r, double i) {`re=r; im=i; }
Design void set(double r, double i) { re=r; im=i; }
Activities double get_re() { return re; }
Tool double get_im() { return im; }
Support int.....
int operator== (const complex &c) const {
SystemC 1.1 };
if ( ( re == c.re ) && ( im == c.im() ) )
return 1;
else
Joachim
Gerlach return 0;
}
};

Joachim Gerlach System-on-Chip Design with SystemC 44

University of
Tübingen Modules & Hierarchie
Department of
Computer
Engineering
q Modules may contain sub-modules (Õ hierarchical structure)

Background q In SC_MODULE:
& Basics
// sub-module declaration
SystemC 1.0 module_type *my_module;
Design
Example A q In the module constructor of SC_MODULE:
Design
Example B // sub-module instantiation and port mapping
SC_CTOR( module_name ) {
Design
Activities my_module = new module_type ( “label”);
Tool my_module -> in1 (sig1);
Support my_module -> in2 (sig2);
my_module
my_module -> out1 (sig3);
SystemC 1.1
} sig1
in1 sig3
out1
in2
Joachim sig2
Gerlach

Joachim Gerlach System-on-Chip Design with SystemC 45

University of
Tübingen Modules & Hierarchie
Department of
Computer
Engineering
q Example:
SC_MODULE( plus ) {
alu SC_MODULE( alu ) {
sc_in<int> i1;
Background sc_in<int> i2; sc_in<int> a;
& Basics
plus sc_in<int> b;
sc_out<int> o1;
a i1 ..... sc_in<int> c;
SystemC 1.0 o1
b i2 sc_out<int> d;
e };
Design
Example A plus *p;
SC_MODULE( minus ) { minus *m;
Design minus sc_in<int> i1;
Example B i1 sc_in<int> i2; sc_signal<int> e;
o1 d sc_out<int> o1;
Design c i2 SC_CTOR( alu ) {
.....
Activities
}; p = new plus ( "PLUS“ );
Tool p->i1 (a);
Support d=(a+b)-c p->i2 (b);
SystemC 1.1 p->o1 (e);

m = new minus ( "MINUS“ );

Joachim (*m) (e,c,d);
Gerlach }
};

Joachim Gerlach System-on-Chip Design with SystemC 46

University of
Tübingen Processes
Department of
Computer
Engineering
q Process Semantics
m Encapsulates functionality
Background
& Basics m Basic unit of concurrent execution

SystemC 1.0 m Not hierarchical

Design
Example A q Process Activation
Design m Processes have sensitivity lists
Example B
m Pocesses are triggered by events on sensitive signals
Design
Activities
q Process Types
Tool
Support m Method (SC_METHOD)
asynchronous block, like a sequential function
SystemC 1.1
m Thread (SC_THREAD)
asynchronous process
Joachim
Gerlach m Clocked Thread (SC_CTHREAD)
synchronous process

Joachim Gerlach System-on-Chip Design with SystemC 47

University of
Tübingen Processes
Department of
Computer
Engineering
SC_METHOD SC_THREAD SC_CTHREAD
triggered by signal events by signal events by clock edge
Background
& Basics
infinite
loop no yes yes
SystemC 1.0

Design execution
no yes yes
Example A suspend
Design suspend wait()
Example B - wait()
& resume wait_until()
Design
Activities construct SC_METHOD(p); SC_THREAD(p); SC_CTHREAD
& (p,clock.pos());
Tool sentisize sensitive(s); sensitive(s);
Support method sensitive_pos(s); sensitive_pos(s); SC_CTHREAD
SystemC 1.1 sensitive_neg(s); sensitive_neg(s); (p,clock.neg());
modeling combinational sequential logic sequential logic
example logic at RT level at higher design
Joachim
Gerlach (hardware) (asynchronous levels
reset, etc.)

Joachim Gerlach System-on-Chip Design with SystemC 48

University of
Tübingen Processes
Department of
Computer
Engineering
q Declaration of member function (in SC_MODULE)
// process declaration
Background void my_process ();
& Basics

SystemC 1.0 q Instantiation (in module constructor of SC_MODULE)

Design // specification of process type and sensitivity
Example A
SC_CTOR( module_name ) {
Design
Example B SC_METHOD( my_process );
sensitive << sig1 << sig2;
Design } plus
Activities

Tool i1
Support q Definition of member function
o1
(in SC_MODULE or somewhere else) i2
SystemC 1.1

// process specification
void module_name::my_process () {
Joachim o1 = i1 + i2
Gerlach .....
}

Joachim Gerlach System-on-Chip Design with SystemC 49

University of
Tübingen Processes
Department of
Computer
Engineering
q Example: SC_METHOD

Background
& Basics SC_MODULE( plus ) { void plus::do_plus() {
sc_in<int> i1; int arg1;
SystemC 1.0
sc_in<int> i2; int arg2;
Design sc_out<int> o1; int sum;
Example A
void do_plus(); arg1 = i1.read();
Design
Example B
arg2 = i2.read();
SC_CTOR( plus ) {
sum = arg1 + arg2;
Design SC_METHOD( do_plus );
o1.write(sum);
Activities sensitive << i1 << i2;
}
Tool }
Support };

SystemC 1.1 void plus::do_plus() {

o1 = i1 + i2;
}
Joachim
Gerlach

Joachim Gerlach System-on-Chip Design with SystemC 50

University of
Tübingen Processes
Department of
Computer
Engineering
q Example: SC_THREAD

Background
& Basics SC_MODULE( plus ) { void plus::do_plus() {
sc_in<int> i1; int arg1;
SystemC 1.0
sc_in<int> i2; int arg2;
Design sc_out<int> o1; int sum;
Example A
void do_plus(); while ( true ) {
Design
arg1 = i1.read();
Example B SC_CTOR( plus ) {
arg2 = i2.read();
Design SC_THREAD( do_plus );
sum = arg1 + arg2;
Activities sensitive << i1 << i2;
o1.write(sum);
Tool }
Support }; wait();
}
SystemC 1.1
}

Joachim
Gerlach

Joachim Gerlach System-on-Chip Design with SystemC 51

University of
Tübingen Processes
Department of
Computer
Engineering
q Example: SC_CTHREAD

Background
& Basics SC_MODULE( plus ) { void do_plus() {
sc_in_clk clk; int arg1;
SystemC 1.0
int arg2;
sc_in<int> i1;
Design int sum;
Example A sc_in<int> i2;
sc_out<int> o1; while ( true ) {
Design
Example B
arg1 = i1.read();
void do_plus();
arg2 = i2.read();
Design sum = arg1 + arg2;
Activities
SC_CTOR( plus ) {
SC_CTHREAD( do_plus, clk.pos() ); o1.write(sum);
Tool }
Support wait();
};
}
SystemC 1.1
}

Joachim
Gerlach

Joachim Gerlach System-on-Chip Design with SystemC 52

University of
Tübingen Waiting and Watching
Department of
Computer
Engineering q Suspend / reactivate process execution (SC_THREAD, SC_CTHREAD)
m Suspension: wait()
Background m Reactivation: event on a sensitive signal
& Basics

SystemC 1.0 q Halt process execution until an event occurs (SC_CTHREAD only)
Design m wait_until ( my_bool_sig.delayed() == true )
Example A

Design q Transfer control to a special code sequenze if a specified condition occurs

Example B
m watching ( reset.delayed() == true )
Design
Activities m Typical example: watching for reset signal

Tool m Global watching: (SC_THREAD, SC_CTHREAD)

Support
- watching condition specified in the module constructor
SystemC 1.1 - control is transfered to the beginning of the process (to be handled there)

m Local watching: (SC_CTHREAD only)

Joachim - allows to specifiy the process region to be watched
Gerlach
- using macros W_BEGIN, W_DO, W_ESCAPE, W_END
- can be nested and combined with global watching

Joachim Gerlach System-on-Chip Design with SystemC 53

University of
Tübingen Cycle-Accurate Simulation Scheduler
Department of
Computer
Engineering Step 1: All clock signals that change their valueat the current time are
assigned their new value.

Background Step2: All SC_METHOD / SC_THREAD processes with inputs that have
& Basics changed are executed. The entire bodies of SC_METHOD
processes are executed. SC_THREAD processes are executed
SystemC 1.0
until the next wait() statement suspends execution.
Design SC_METHOD / SC_THREAD processes are not executed in a
Example A fixed order.

Design Step3: All SC_CTHREAD processes that are triggered have their
Example B outputs updated and are saved in a queue to be executed in
step 5. All outputs of SC_METHOD / SC_THREAD processes
Design
Activities that were executed in step 1 are also updated.

Tool Step 4: Step 2 and step 3 are repeated until no signal changes ist value.
Support
Step 5: All SC_CTHREAD processes that were triggered and queued in
SystemC 1.1 step 3 are executed. There is no fixed execution order of these
processes. Their outputs are updated at the next active edge
(when step 3 is executed), and therefore are saved internally.
Joachim
Gerlach
Step6: Simulation time is advanced to the next clock edge and the
scheduler goes back to step 1.

Joachim Gerlach System-on-Chip Design with SystemC 54

TM
SYSTEMC

Design Example A
University of Tübingen
Wilhelm-Schickard-Institut
Department of Computer Engineering
University of
Tübingen SystemC: Example-1
Department of
Computer
Engineering
Example

Background
Two processes (process_1 and process_2)
& Basics alternately incrementing an integer value
SystemC 1.0

Design process_1
Example A
int
a +5 b
Design
bool
Example B ready_a ready_b
Design
Activities
process_2
Tool
Support int
b +3 a
SystemC 1.1 bool
ready_b ready_a

Wolfgang
Rosenstiel

Joachim Gerlach System-on-Chip Design with SystemC 56

University of
Tübingen Source Code File Structure
Department of
Computer
Engineering

systemc.h process_1.h process_2.h

Background
& Basics

SystemC 1.0

Design
Example A
process_1.cc process_2.cc main.cc
Design
Example B
library
Design
Activities

Tool
Support g++

SystemC 1.1

a.out
Wolfgang
Rosenstiel
executable = simulation

Joachim Gerlach System-on-Chip Design with SystemC 57

University of
Tübingen Module: process_1
Department of
Computer
Engineering
// header file: process_1.h

SC_MODULE( process_1 ) {
Background
& Basics // Ports
// implementation file: process_1.cc
sc_in_clk clk;
SystemC 1.0 sc_in<int> a; #include "systemc.h"
sc_in<bool> ready_a; #include "process_1.h"
Design sc_out<int> b;
Example A sc_out<bool> ready_b; void process_1::do_process_1()
{
Design // Process functionality int v;
Example B void do_process_1();
while ( true )
Design // Constructor {
Activities SC_CTOR( process_1 ) { wait_until( ready_a.delayed() == true );
SC_CTHREAD( do_process_1 , clk.ps() ); v = a.read();
Tool } v += 5;
Support cout << "P1: v = “ << v << endl;
}; b.write( v );
SystemC 1.1 ready_b.write( true );
wait();
ready_b.write( false );
Wolfgang }
Rosenstiel }

Joachim Gerlach System-on-Chip Design with SystemC 58

University of
Tübingen Module: process_2
Department of
Computer
Engineering
// header file: process_2.h

SC_MODULE( process_2 ) {
Background
& Basics // Ports
// implementation file: process_2.cc
sc_in_clk clk;
SystemC 1.0 sc_in<int> a; #include "systemc.h"
sc_in<bool> ready_a; #include "process_2.h"
Design sc_out<int> b;
Example A sc_out<bool> ready_b; void process_2::do_process_2()
{
Design // Process functionality int v;
Example B void do_process_2();
while ( true )
Design // Constructor {
Activities SC_CTOR( process_2 ) { wait_until( ready_a.delayed() == true );
SC_CTHREAD( do_process_2 , clk.ps() ); v = a.read();
Tool } v += 3;
Support cout << "P2: v = “ << v << endl;
}; b.write( v );
SystemC 1.1 ready_b.write( true );
wait();
ready_b.write( false );
Wolfgang }
Rosenstiel }

Joachim Gerlach System-on-Chip Design with SystemC 59

University of
Tübingen Top-Level Module: main
Department of
Computer
Engineering
// implementation file: main.cc

#include "systemc.h"
Background #include "process_1.h"
& Basics #include "process_2.h"

int sc_main (int ac,char *av[])

SystemC 1.0 {
sc_signal<int> s1 ( “Signal-1“ );
Design sc_signal<int> s2 ( “Signal-2“ );
Example A sc_signal<bool> ready_s1 ( “Ready-1“ );
sc_signal<bool> ready_s2 ( “Ready-2“ ); process_2 p2 ( “P2“ );
Design
sc_clock clock( "Clock“ , 20 , 0.5 , 0.0 ); p2.clk( clock );
Example B
p2.a( s2 );
process_1 p1 ( “P1“ ); p2.ready_a( ready_s2 );
Design
p1.clk( clock ); p2.b( s1 );
Activities
p1.a( s1 ); p2.ready_b( ready_s1 );
Tool p1.ready_a( ready_s1 );
p1.b( s2 ); s1.write(0);
Support s2.write(0);
p1.ready_b( ready_s2 );
ready_s1.write(true);
SystemC 1.1 ready_s2.write(false);

sc_start(100000);
Wolfgang return 0;
Rosenstiel }

Joachim Gerlach System-on-Chip Design with SystemC 60

University of
Tübingen Simulation Results
Department of
Computer
Engineering
q Simulation output
SystemC (TM) Version 1.0 --- Apr 4 2000 10:12:32
Background
ALL RIGHTS RESERVED
& Basics
Copyright (c) 1988-2000 by Synopsys, Inc.
SystemC 1.0 P1: v = 5
P2: v = 8
Design P1: v = 13 simulation speed:
Example A P2: v = 16
P1: v = 21
Design P2: v = 24 simulation of 100.000 cycles
Example B P1: v = 29 takes about 0.08 seconds
P2: v = 32
Design P1: v = 37 on a Sun Ultra Sparc 5
Activities P2: v = 40 (384 MByte main memory)
P1: v = 45
Tool P2: v = 48
P1: v = 53 (output skipped) comparison to
Support
P2: v = 56 simulation speed of SystemC 0.9:
SystemC 1.1 P1: v = 61
P2: v = 64
P1: v = 69 simulation of 100.000 cycles
P2: v = 72
Wolfgang P1: v = 77
takes about 0.31 seconds
Rosenstiel P2: v = 80 on the same machine
.....

Joachim Gerlach System-on-Chip Design with SystemC 61

TM
SYSTEMC

Design Example B
University of Tübingen
Wilhelm-Schickard-Institut
Department of Computer Engineering
University of
Tübingen SystemC Design Example
Department of
Computer
Engineering
q Background:

Background
& Basics
SystemC C / C++
SystemC 1.0

Design
Example A
„top-down“
Design „bottom-up“
Example B

Design
Activities
HDL
Tool
„non-coded“ SystemC
Support

SystemC 1.1
Transforming HDL into SystemC Transforming C/C++ into SystemC
Creating new designs in SystemC • Many algorithms exist in C/C++
Joachim
Gerlach
• Many standardization committees
• (e.g., ISO) use C specifications

Joachim Gerlach System-on-Chip Design with SystemC 63

University of
Tübingen SystemC Design Example
Department of
Computer
Engineering
q Application:
JPEG compression and decompression stream
Background
& Basics

SystemC 1.0
JPEG Compressed
Reader Encoder
Design data stream
Example A Output Picture
(pgm)
Design Input Picture
Example B (pgm)
JPEG
Design Decoder Writer
Activities

Tool
Support

SystemC 1.1 q Reference implementation:

m 16 modules, approx. 950 lines of C++ code
Joachim m by T. Thissenhusen, TU Dresden, Germany
Gerlach

Joachim Gerlach System-on-Chip Design with SystemC 64

University of
Tübingen SystemC Design Example
Department of
Computer input pgm-file start
Engineering

Reader
Background
& Basics

SystemC 1.0
DCT IRLEH
Design
Example A
Encoder
Design Quant IZigZag
Example B

Design
Activities ZigZag IQuant
Tool Decoder
Support

SystemC 1.1 RLEH IDCT

Joachim Writer
Gerlach

output pgm-file

Joachim Gerlach System-on-Chip Design with SystemC 65

University of
Tübingen SystemC Design Example
Department of
Computer
Engineering
Encoder
struct Block {
Background char data[8][8];
& Basics ....
}; DCT data_in start ready
SystemC 1.0
Coeff_8x8 bool bool
Design
Example A struct Coeff_8x8 {
short data[8][8];
Design .... Quant clk
Example B };
ZigZag
Design
Activities
struct Matrix_64x12 { ZigZag
Tool
Support
short data[64];
.... Matrix_64x12 bool bool
SystemC 1.1 };
data_out data data_ok
RLEH _out
Joachim _ready
Gerlach char data;

Joachim Gerlach System-on-Chip Design with SystemC 66

University of
Tübingen SystemC Design Example
Department of
Computer input pgm-file start
Engineering

data
data
ready ready
Reader data
data
ready ready
Background
& Basics
data data ready
SystemC 1.0 ready
DCT IRLEH
Design data data data data
ready ready ready ready
Example A
Encoder
Design Quant IZigZag
Example B
data data data data ready data data
ready ready ready ready ready
Design
Activities ZigZag IQuant
Tool data data Decoder data data
ready ready ready ready
Support

SystemC 1.1 RLEH data data ready IDCT

ready

data data ready data data ready

Joachim ready Writer ready
Gerlach

output pgm-file

Joachim Gerlach System-on-Chip Design with SystemC 67

TM
SYSTEMC

Design Activities
University of Tübingen
Wilhelm-Schickard-Institut
Department of Computer Engineering
University of
Tübingen Design Activities
Department of
Computer
Engineering

q Modeling
Background m Module for “zigzag”computation
& Basics

SystemC 1.0 q Simulation

Design m Generation and run of an executable specification
Example A

Design
Example B q Debugging
Design m Techniques for checking the functionality of the system
Activities

Tool
Support

SystemC 1.1

Joachim
Gerlach

Joachim Gerlach System-on-Chip Design with SystemC 69

University of
Tübingen Modeling
Department of
Computer
Engineering void zigzag::do_zigzag() { zigzag.cc
Coeff_8x8 fuv;
Matrix_64x12 result;
#include <systemc.h> zigzag.h unsigned char u, v, a, dir;
#include "global.h" while(true) {
Background ready.write(true);
& Basics SC_MODULE(zigzag) { data_out_ready.write(false);
wait_until(start.delayed()==true);
sc_in_clk clk; ready.write(false);
SystemC 1.0
sc_in<Coeff_8x8> data_in; fuv = data_in.read();
sc_in<bool> start; // zigzag
Design sc_in<bool> data_ok; u = 0; v = 0;
Example A sc_out<Matrix_64x12> data_out; dir = 1; // dir == 1: upwards, dir == 0: downwards
sc_out<bool> ready; for ( a = 0; a < 64; a++ ) {
Design sc_out<bool> data_out_ready; result.put ( a, (WORD) (fuv.get (v,u) ) );
Example B void do_zigzag(); if ( v == 0 )
if ( dir ) { u++; dir = 0; }
SC_CTOR(zigzag) { else { u--; v++; }
Design SC_CTHREAD(do_zigzag,clk.pos()); else if ( v == 7 )
Activities } if ( !dir ) { u++; dir = 1; }
}; else { u++; v--; }
else if ( u == 0 )
Tool if ( !dir ) { v++; dir = 1; }
else { u++; v--; }
Support else if ( u == 7 )
if ( dir ) { v++; dir = 0; }
SystemC 1.1 else { u--; v++; }
else
if ( dir ) { u++; v--; }
else { u--; v++; }
}
Joachim data_out.write(result);
Gerlach data_out_ready.write(true);
wait_until(data_ok.delayed()==true);
}
}

Joachim Gerlach System-on-Chip Design with SystemC 70

University of
Tübingen Simulation
Department of
Computer
Engineering
q Generation of an executable specification

Background
& Basics systemc.h reader.h ...... writer.h
SystemC 1.0

Design
Example A

Design
reader.cc ...... writer.cc jpeg.cc
Example B

Design library
Activities

Tool
Support
g++
SystemC 1.1

Joachim
Gerlach run

executable = simulator

Joachim Gerlach System-on-Chip Design with SystemC 71

University of
Tübingen Simulation
Department of
Computer
Engineering
q Simulation control
m Simulation start:
Background
& Basics sc_start() / sc_start(n) from the top-level function sc_main()
SystemC 1.0 m Simulation stop:
Design sc_stop() from within any process
Example A

Design q Advanced simulation control:

Example B
“self-made” clock by sc_initialize() and sc_cycle(n)
Design
Activities true
sc_clock my_clock (“CLK”, 20, 0.5 ); false
Tool 0 10 20 30 40
Support
sc_start(200); sc_initialize();
SystemC 1.1 for (int i=0; i<=200; i++) {
clock = 1;
sc_cycle(10);
Joachim
Gerlach clock = 0;
sc_cycle(10);
}

Joachim Gerlach System-on-Chip Design with SystemC 72

University of
Tübingen Simulation
Department of
Computer
Engineering
q Running the executable specification

Background
& Basics > ./run motorbike.pgm motorbike2.pgm

SystemC 1.0 SystemC (TM) Version 1.0 --- May 22 2000 14:21:01
ALL RIGHTS RESERVED
Design Copyright (c) 1988-2000 by Synopsys, Inc.
Example A
Comment: CREATOR: XV Version 3.10a Rev: 12/29/94
Design SystemC: simulation stopped by user.
Example B >
>
Design
Activities

Tool
Support

SystemC 1.1

Joachim
Gerlach

Joachim Gerlach System-on-Chip Design with SystemC 73

University of
Tübingen Simulation
Department of
Computer
Engineering
q Results of an executable run

Background input picture compression output picture

& Basics (motorbike.pgm) decompression (motorbike2.pgm)
stream
SystemC 1.0
JPEG
Design Reader Encoder
Example A

Design
Example B JPEG
Decoder Writer

Design
Activities

Tool
Support

SystemC 1.1

Joachim
Gerlach

Joachim Gerlach System-on-Chip Design with SystemC 74

University of
Tübingen Debugging
Department of
Computer
Engineering
q Observation of simulation results

Background
& Basics q Adding (C/C++) assertions/debug outputs to the source code
SystemC 1.0

Design q Using SystemC debugging features

Example A

Design
Example B q Using standard debugging tools (gdb, Purify,...)
Design
Activities

Tool
Support

SystemC 1.1

Joachim
Gerlach

Joachim Gerlach System-on-Chip Design with SystemC 75

University of
Tübingen Debugging
Department of
Computer
Engineering
q Adding debug outputs to the source code

Background void zigzag::do_zigzag() {

& Basics zigzag.cc
.....
SystemC 1.0
static int no_of_zigzags = 0;
Design while(true) {
Example A
.....
Design // zigzag computation
Example B .....
Design no_of_zigzags++;
Activities cout << „number of zigzags:“ << no_of_zigzags << endl;

Tool .....
Support }
}
SystemC 1.1

Joachim
Gerlach

Joachim Gerlach System-on-Chip Design with SystemC 76

University of
Tübingen Debugging
Department of
Computer
Engineering
q Running the executable specification

Background
& Basics
> ./run motorbike.pgm motorbike2.pgm

SystemC 1.0 SystemC (TM) Version 1.0 --- May 22 2000 14:21:01
ALL RIGHTS RESERVED
Design Copyright (c) 1988-2000 by Synopsys, Inc.
Example A Comment: CREATOR: XV Version 3.10a Rev: 12/29/94
Design
number of zigzags: 1
Example B number of zigzags: 2
number of zigzags: 3
Design number of zigzags: 4
Activities .....
number of zigzags: 1099
Tool
number of zigzags: 1100
Support
number of zigzags: 1101
SystemC 1.1 number of zigzags: 1102
SystemC: simulation stopped by user.
>
Joachim >
Gerlach

Joachim Gerlach System-on-Chip Design with SystemC 77

University of
Tübingen Debugging
Department of
Computer
Engineering
q Using SystemC debugging features: sc_time_stamp()

Background
void zigzag::do_zigzag() { zigzag.cc
& Basics
.....
SystemC 1.0
static int no_of_zigzags = 0;
Design while(true) {
Example A
.....
Design // zigzag computation
Example B .....
Design no_of_zigzags++;
Activities cout << „cycle: “ << sc_time_stamp();
cout << „ - number of zigzags:“ << no_of_zigzags << endl;
Tool
Support .....
}
SystemC 1.1 }

Joachim
Gerlach

Joachim Gerlach System-on-Chip Design with SystemC 78

University of
Tübingen Debugging
Department of
Computer
Engineering
q Running the executable specification

Background
& Basics
> ./run motorbike.pgm motorbike2.pgm

SystemC 1.0 SystemC (TM) Version 1.0 --- May 22 2000 14:21:01
ALL RIGHTS RESERVED
Design Copyright (c) 1988-2000 by Synopsys, Inc.
Example A Comment: CREATOR: XV Version 3.10a Rev: 12/29/94
Design
cycle: 5 - number of zigzags: 1
Example B cycle: 8 - number of zigzags: 2
cycle: 11 - number of zigzags: 3
Design cycle: 14 - number of zigzags: 4
Activities .....
cycle: 3299 - number of zigzags: 1099
Tool
cycle: 3302 - number of zigzags: 1100
Support
cycle: 3305 - number of zigzags: 1101
SystemC 1.1 cycle: 3308 - number of zigzags: 1102
SystemC: simulation stopped by user.
>
Joachim >
Gerlach

Joachim Gerlach System-on-Chip Design with SystemC 79

University of
Tübingen Debugging
Department of
Computer
Engineering
q Using SystemC debugging features: waveform tracing

Background
& Basics
int sc_main( int argc, char *argv[] ) jpeg.cc
{
SystemC 1.0 .....

Design // waveform tracing

Example A if ( (argc == 4) && (strcmp(argv[3],"w") == 0) ) {

sc_trace_file* tf = sc_create_wif_trace_file( „wave“ );

Design
Example B sc_trace( tf, clk.signal(), „clock“ );
sc_trace( tf, encoder_is_ready, „encoder_is_ready“ );
Design sc_trace( tf, orig_data_ready, „start_dct“ );
Activities
sc_trace( tf, e.data_out_ready_1, „start_quant“ );
sc_trace( tf, e.data_out_ready_2, „start_zigzag“ );
Tool
Support sc_trace( tf, e.data_out_ready_3, „start_rleh“ );
sc_trace( tf, decoder_is_ready, „decoder_is_ready“ );
SystemC 1.1 sc_trace( tf, comp_data_ready, „start_idct“ );
sc_trace( tf, d.data_out_ready_1, „start_iquant“ );
sc_trace( tf, d.data_out_ready_2, „start_izigzag“ );
Joachim sc_trace( tf, d.data_out_ready_3, „start_irleh“ );
Gerlach }
.....
}

Joachim Gerlach System-on-Chip Design with SystemC 80

University of
Tübingen Debugging
Department of
Computer
Engineering
q Running the executable specification (with “w” parameter)

Background
& Basics
> ./run motorbike.pgm motorbike2.pgm w

SystemC 1.0 SystemC (TM) Version 1.0 --- May 22 2000 14:21:01
ALL RIGHTS RESERVED
Design Copyright (c) 1988-2000 by Synopsys, Inc.
Example A WARNING: Default time step (1 s) is used for WIF tracing.
Design
Comment: CREATOR: XV Version 3.10a Rev: 12/29/94
Example B SystemC: simulation stopped by user.
>
Design > viewer wave.awif &
Activities >
>
Tool
Support

SystemC 1.1

Joachim
Gerlach

Joachim Gerlach System-on-Chip Design with SystemC 81

TM
SYSTEMC

Tool Support
University of Tübingen
Wilhelm-Schickard-Institut
Department of Computer Engineering
University of
Tübingen Synopsys SystemC Compiler
Department of
Computer
Engineering
q SystemC for system modeling

Background
& Basics SystemC
SystemC 1.0
Modeling
Design Constructs
Example A

Design
C/C++ Testbench C/C++ Software
Example B

Design
Activities
C/C++ Hardware/System System
Tool
Support

SystemC 1.1 Standard

C++ Compiler
Wolfgang
Rosenstiel
Executable = Simulator != Debugger

Joachim Gerlach System-on-Chip Design with SystemC 83

University of
Tübingen Synopsys SystemC Compiler
Department of
Computer
Engineering
q SystemC Compiler C++ synthesis in the HW flow

Background
& Basics

SystemC 1.0
Model using SystemC
Design
Example A

Design
Example B
SystemCTM Compiler
db form
Design db form (This flow is not supported currently)
Activities db or HDL
format
Tool Behavioral synthesis RTL synthesis
Support

SystemC 1.1

Wolfgang
Gate level netlist
Rosenstiel

Joachim Gerlach System-on-Chip Design with SystemC 84

University of
Tübingen Synopsys SystemC Compiler
Department of
Computer
Engineering
q Refinement for implementation

Background System Specification

& Basics

SystemC 1.0

Design
Refine Structure
Example A • Partition into blocks that will be
independently synthesized/refined
Design
Example B • Refine interfaces for communication
Design
Activities

Tool
Refine Control Refine Data
Support • Specify I/O protocol • Use bit-true types
•Specify clock domains • Select appropriate
SystemC 1.1
• Specify latency, throughput bit widths
• Specify FSM & datapath for RTL
Wolfgang
Rosenstiel

System Implementation

Joachim Gerlach System-on-Chip Design with SystemC 85

University of
Tübingen Synopsys SystemC Compiler
Department of
Computer
Engineering
q Behavioral Level Flow

Background yes no
& Basics Behavioral
Code? Timed DB File
Code
SystemC 1.0 Latency/Pipeline
Design SystemC Compiler Remove Constraints
Example A Design
Schedule
Design
Example B no
Initial Constraints SystemC View
Design OK? Reports
Activities yes
Check Design
Tool
Support Cycle-Accurate Cycle-Accurate DB
Time/Area Estimates HDL
SystemC 1.1
HDL Compile
Co-Simulation
Wolfgang Timed DB File Gate Level Netlist
Rosenstiel

Timed DB Generation High-Level Synthesis

Joachim Gerlach System-on-Chip Design with SystemC 86
University of
Tübingen Synopsys SystemC Compiler
Department of
Computer
Engineering
q Hardware Implementation Flow

Background
& Basics
Functional
SystemC 1.0 Design
Refinement IQ Block
Design (communication,
Example A timing, memories)
Design Architectural SystemC Compiler
Example B Design
Refinement Behavioral Flow
Design (resources, scheduling,
Activities allocation, FSM design)
Tool Controller
Support
RT Level
Design
SystemC 1.1
SystemC Compiler
RTL Flow
Wolfgang
Rosenstiel
Gate Level
Design

Joachim Gerlach System-on-Chip Design with SystemC 87

University of
Tübingen Synopsys SystemC Compiler
Department of
Computer
Engineering
q Benefits

Background m Rapid time to market

& Basics
– fast refinement from functional model behavioral model
SystemC 1.0

Design
– accommodating late spec changes
Example A

Design
m Graphical analysis of design
Example B
m High quality of results
Design
Activities
– tight integration into Synopsys synthesis flow
Tool
Support – flexibility for datapath components
SystemC 1.1

Wolfgang
Rosenstiel

Joachim Gerlach System-on-Chip Design with SystemC 88

University of
Tübingen CoWare N2C
Department of
Computer
Engineering
q Gaps in System Design

Background
& Basics

SystemC 1.0

Design
Example A

Design
Example B

Design
Activities

Tool
Support

SystemC 1.1

Wolfgang
Rosenstiel

Joachim Gerlach System-on-Chip Design with SystemC 89

University of
Tübingen CoWare N2C
Department of
Computer
Engineering
q System-Level Design with CoWare N2C

Background
& Basics

SystemC 1.0

Design
Example A

Design
Example B

Design
Activities

Tool
Support

SystemC 1.1

Wolfgang
Rosenstiel

Joachim Gerlach System-on-Chip Design with SystemC 90

University of
Tübingen CoWare N2C
Department of
Computer
Engineering
q N2C Workbench
m Hierarchical design browser (architecture, functionality)
Background
& Basics
m Source code editor (context sensitive)
SystemC 1.0
m Project manager (partition management)
Design
Example A

Design q CoWare Support

Example B
m CoWare N2C supports a top-down design flow for HW/SW
Design
Activities co-design from UTF to RTL
Tool m Co-simulation of different languages
Support

SystemC 1.1
m Fast design exploration and HW/SW partitioning
m Allows for efficient IP reuse and delivery
Wolfgang
Rosenstiel
m Provides synthesis of communication

Joachim Gerlach System-on-Chip Design with SystemC 91

University of
Tübingen System Compiler (C Level Design)
Department of
Computer
Engineering
q System Compiler
m supports full ANSI
Background
& Basics C and C++
native Class-based C++
m provides complex data C/C++ (System C++)
SystemC 1.0

Design
structures, static pointer
Example A analysis, abstraction, bit-accurate (fixed and floating)
Design
hierarchy simulation libraries
Example B
m output is RT level HDL native C/C++ CSim/System C++
Design (VHDL or Verilog) simulation simulation
Activities

Tool q CSim System Compiler

Support
C/C++ synthesis
SystemC 1.1 m executable specification
m discrete event simulation RTL
Wolfgang HDL
Rosenstiel m abstraction: temporal time,
data values, functionality

Joachim Gerlach System-on-Chip Design with SystemC 92

University of
Tübingen A|RT Builder (Frontier Design)
Department of
Computer system specification datapath resources
Engineering embedded software (arithmetic, memory)

legacy HDL
Background HWhw
& Basics HW
Resource vendor HDL
ANSI resource
Resource
Library
C Library
library
SystemC 1.0

Design
Example A create
edit/compile
edit/compile createarchitecture
architecture
Design
Example B map
maptotoarchitecture
architecture
Design
Activities source code schedule
scheduleoperations
operations architecture
tuning optimization
Tool
Support performance analysis

SystemC 1.1 build

buildRTL
RTLcode
code

logic synthesis
Wolfgang
Rosenstiel
FPGA ASIC

Joachim Gerlach System-on-Chip Design with SystemC 93

TM
SYSTEMC

SystemC 1.1
Outlook
University of Tübingen
Wilhelm-Schickard-Institut
Department of Computer Engineering
University of
Tübingen SystemC 1.1 Design Flow
Department of
Computer
Engineering
Matlab C++ SDL Esterel ......

Background
& Basics functional
SystemC decomposition
1.1
SystemC 1.0 untimed
UTF functional
Design design exploration
Example A assign
performance analysis „execution time“
hw/sw partitioning
Design timed
Example B TF functional
Design hw/sw partitioning
Activities refine communication

Tool bus cycle

task Abstr.
Support partitioning RTOS BCA accurate
SystemC 1.1 refine
behavior

target
cycle
Joachim RTOS/core
RTOS RTL accurate
Gerlach
software hardware

Joachim Gerlach System-on-Chip Design with SystemC 95

University of
Tübingen Design Levels in SystemC 1.1
Department of
Computer
Engineering
q UTF: UnTimed Functional
m Functional decomposition of a system
Background m Architecture, timing, inter-block communication is abstracted
& Basics
m Maximally sequential form by RPC (Remote Procedure Call)
SystemC 1.0
m RPC: abstract (master/slave-)ports, multi-point link objects
Design
Example A

Design
q TF: Timed Functional
Example B m RPC also, but processes may be assigned a run time
Design
Activities
q BCA: Bus Cycle Accurate
Tool
Support
m Abstract ports refined to bus ports with data, adress, control
terminals and communication protocols
SystemC 1.1

q CA: Cycle Accurate

Joachim
Gerlach m SystemC 1.0 level

Joachim Gerlach System-on-Chip Design with SystemC 96

TM
SYSTEMC

Questions
& Answers
University of Tübingen
Wilhelm-Schickard-Institut
Department of Computer Engineering