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Digital Design Flow: 1. Verilog Code + Simulation

The document describes a digital design flow involving Verilog simulation, synthesis, and physical design using place and route tools. Key steps include: 1. Writing Verilog code and simulating using a simulator. 2. Synthesizing the Verilog using a synthesis tool to produce a netlist. 3. Performing physical design including floorplanning, placement, routing, and clock tree synthesis using place and route tools to produce a final routed layout.

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KhakhariaHétál
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72 views3 pages

Digital Design Flow: 1. Verilog Code + Simulation

The document describes a digital design flow involving Verilog simulation, synthesis, and physical design using place and route tools. Key steps include: 1. Writing Verilog code and simulating using a simulator. 2. Synthesizing the Verilog using a synthesis tool to produce a netlist. 3. Performing physical design including floorplanning, placement, routing, and clock tree synthesis using place and route tools to produce a final routed layout.

Uploaded by

KhakhariaHétál
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOC, PDF, TXT or read online on Scribd
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Digital Design Flow

[Contact: Gagandeep Singh(9828463967), Jitin S(9660004330)]

1. Verilog Code + Simulation >source /edatools/scripts/mentor/model.cshrc >vsim & FileNewProject Add .v files (main file + testbench) to project, compile & simulate Verify results in wave window 2. Synthesis 1. Make a folder <rc_compiler> in your home directory >cd rc_compiler i) Make four folders in your working folder rc_compiler as rtl, results, scripts, com_files ii) Put the verilog code in the rtl folder iii)Copy com_files and scripts from /assignments/mh123046/rc_compiler/scripts iv)Edit the script accordingly >source /edatools/scripts/cadence/rc81.cshrc >rc f ./scripts/top01_golden.g |tee ./results/update.log For P&R you will need final_NL.v (optimized netlist output from RC Compiler) and Timing.sdc (synopsys design constraints) files. (both in the results folder) 3. Place & Route (P&R) >source /edatools/scripts/cadence/encounter.cshrc >encounter -Xmode Steps:
1. DesignDesign Import

2. Design import window will appear. In this: a) In Design tab: # Verilog Files: < .v file in your results folder> # Click Auto Assign # LEF Files: Path/edatools/dk/umc/vst/standard_cells/silicon_ensemble/header_6lm_5.4.lef & /umcl18g300t3_6lm_5.4.lef # Max Timing Libraries: /edatools/dk/umc/vst/standard_cells/tlf/125C.tlf # Min Timing Libraries: /edatools/dk/umc/vst/standard_cells/tlf/OC.tlf # Common Timing Libraries: /edatools/dk/umc/vst/standard_cells/tlf/25C.tlf b) In Timing tab: # Timing Constraint File: <.sdc file in your results folder> c) In Power tab:

# Power Nets: vdd d) In Misc. tab: # cdB File:

# Ground Nets: gnd

Path/edatools/cadence/soc41/share/examples/celtic_examples/Training/library/generic _018u_125C_SS.cdB Save this configuration as a .conf file.


3. Floorplan Specify Floorplan

Specify Floorplan window will appear: Aspect Ratio: 0.90 Core Utilization: 0.50 Core Margins By: Core to IO BoundaryAll values: 15(Core to Left, Right, Top, Bottom) 4. FloorplanPower planningAdd Rings In Basic tab: Ring ConfigurationAll Widths= 5, Spacing= 0.3
5. FloorplanGlobal Net Connections

#Tie High, To Global Net: vdd, Add to List #Tie low, To Global Net: gnd, Add to list.
6. FloorplanPower PlanningAdd Stripes

In Basic tab: #Click Horizontal, Layer: ME1 #Width: .5, Spacing: 4.5 #Set-to-set distance: 4.5 #Relative from core or selected area: Y from top, Y from bottom: 5
7. PlacePlace

#Timing Driven
8. RouteSRoute 9. RouteNanoRoute 10. TimingTiming Analysis

#Check the Worst Negative Slack(WNS) in qsh window [To optimize this we have to generate a clock tree.]
11. ClockCreate Clock Tree Spec

#Open final_NL.v in results folder #Look for BUFF or INV & put their ID in Buffer footprint & Inverter footprint respectively.
12. ClockSpecify Clock Tree 13. ClockSynthesize Clock Tree 14. TimingOptimization 15. Verify<Verify Everything> 16. DesignSaveNetlist (simulate it in any verilog simulator to verify layout design)

OR DesignSaveGDS( import the gds in icfb to extract a .cir from the layout design)

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