United International University (UIU)
Dept. of Electrical and Electronic Engineering (EEE)
Course: VLSI Design Lab (EEE 442)
Experiment 4: Physical Design of a Counter
Introduction:
1. Switch to csh, this will also setup your cadence tools environment variables
csh
2. Create the lab directory and few other sub-directories under your work area:
mkdir lab4
cd lab4
mkdir lib constraints lef physical_design netlist
3. Copy the gate level netlist from previous lab into the netlist/ sub-directory
cp ../lab3/synthesis/cntr8bit_netlist.v netlist/
4. Copy the SDC constraint from previous lab into the constraints/ sub-directory
cp ../lab3/synthesis/cntr8bit.sdc constraints /
5. Copy the .lib files from previous lab into the lib/ sub-directory
cp ../lab3/lib/*.lib lib/
6. Copy the LEF (Library Exchange Format) file from ~sahmed/eee442/lab4/lef/
cp ~sahmed/eee442/lab4/lef/all.lef lef/
7. Go to physical_design/ and invoke Encounter Tool to do the Place & Route the design. This will launch the
Encounter Tool in the GUI mode.
cd physical_design
encounter
DESIGN IMPORT:
8. Click on File Import Design menu option. This will open the Design Import window.
9. Under Netlist: option choose Verilog. Click on the browse button to select the gate level netlist from the
netlist/ sub-directory. Be sure that your netlist is correct.
10. Under Top Cell: option select Auto Assign:
11. Under Technology/Physical Libraries: option select LEF Files: Click on the browse button and select all.lef file
from lef/ sub-directory
12. Under Power option use VDD as power Nets: VSS as Ground Nets:
13. Under analysis Configuration option click on the Create Analysis Configuration button.
14. An MMMC Browser window will open.
15. Double click on Library Sets. Add Library Set window will open. Name: it as max_timing and click on ‘Add…’
button under ‘Timing Library Files’
16. Set max_timing to ‘slow.lib’ and min_timing to ‘fast.lib’ under the lib/ sub-directory.
17. Double click on Delay Corners. Add Delay Corner window will appear. Name: it as min_delay. In the ‘Library
Set’ option under ‘Attributes’, scroll to min_timing and click ‘OK’
18. Similarly set max_delay to max_timing.
19. Double click on Constraints Modes. Add Constraint Mode window will open. Name: it as counter_constraints
and click on ‘Add…’ button under ‘CDS Constraint Files’
20. Set counter_constraints to ‘cntr8bit.sdc’ under constraints/ sub-directory.
21. Double click on Analysis Views. Add Analysis View window will open. Name: it as worst_case and select
max_delay for Delay Corner and click ‘OK’
22. Similarly set best_case to min_delay.
23. Double click on Setup Analysis Views. Add Setup Analysis Views window will open. Set the Analysis View to
worst_case. Click ‘OK’
24. Double click on Hold Analysis Views. Add Hold Analysis Views window will open. Set the Analysis View to
best_case. Click ‘OK’
25. MMMC Browser will look as below: Click on ‘Save & Close’.
26. Save MMMC View Definition File window will open. Provide the File name: as Default.view and click on ‘Save’
27. Click ‘OK’ on the Design Import window. This will load the design into Encounter
FLOOR PLANNING
28. Click Floorplan Specify Floorplan menu option. This will open the ‘Specify Floorplan’ window.
29. Select aspect ratio as per requirement. Give some dimension in ‘Core to Left’, ‘Core to Right’, ‘Core to Top’
and ‘Core to Bottom’. (Remember the values are in µm) to create space for Power Rings. After defining code
are, click ‘OK’
POWER PLANNING
30. Click on Power Power Planning Add Rings menu option. This will open ‘Add Rings’ window
31. Type/Select VDD and VSS nets under the Net(s) option.
32. Select top/bottom layers as Metal5, left/right layers as Metal6. Make sure the metal layer names match with
that of all.lef file in lef/ sub-directory. Set the width/space as per requirement (unit is in µm) and taking the
space between core boundary and I/O pad consideration. Select the option for offset as ‘Center in channel’
and click ‘OK’.
33. Power ring will be created between core boundary and IO/Die boundary.
34. Click Power Power Planning Add Stripe menu option. This will open ‘Add Stripes’ window
35. Type/Select VDD and VSS nets under the Net(s) option.
36. Select Layer: as Metal6 and Direction: as Vertical. Make sure the metal layer names and direction match with
that of all.lef. Set width/spacing as per requirement (unit is in µm). Choose one of the Set Pattern, use Core
ring as the Stripe Boundary, set the First/Last Stripe staring from left. Click ‘OK’.
37. Vertical power stripe will be created.
38. Perform steps 34, 35 and 36 to create horizontal stripes if needed.
39. Click Route Special Route menu option. This will open ‘SRoute’ window
40. Type/Select VDD and VSS nets under the Net(s) option.
41. Choose any of the options IFollow Pins for standard cells) that you want to ruote under SRoute
42. Choose the Top/Bottom Layer and other option as needed. Click ‘OK’
43. This will create the standard cell rails and others if chosen
PLACEMENT
44. Click Place Place Standard Cells menu option. This will open ‘Place’ window
45. Select ‘Run Full Placement’, choose ‘Include Pre-Place Optimization’ under Optimization Option. Click ‘OK’
46. Click on the Physical View to see the standard cells.
PRE-CTS TIMING
47. Click Timing Report Timing menu option. This will open ‘Timing Analysis’ window
48. Select ‘Pre-CTS’ under Design Stage and ‘Setup’ under Analysis Type. Click ‘OK’
49. This will display the timing information on the encounter terminal. Carefully check the Worst Negative Slack
(WNS) and Total Negative Slack (TNS).
50. If there are WNS/TNS, click on Optimize Optimize Design menu option. This will open ‘Optimization’
window
51. Select ‘Pre-CTS’ under Design Stage and ‘Setup’, ‘Max Cap’ and ‘Max Tran’ under Optimization Type. Click
‘Ok’. This will optimize the design. Check timing again. Repeat until timing is met.
CLOCK TREE SYNTHESIS
52. Click Clock Synthesize Clock Tree…’ menu option. This will open ‘Synthesize Clock Spec’ window
53. Click on ‘Gen Spec…’ This will open ‘Generate Clock Spec’ window
54. From Cells List select all cells starting with ‘CLK’ and click on ‘Add’ button to add them to the Selected Cells.
Give a name for the Output Specification File: and click ‘OK’.
55. Give a name for the Result Directory: in the ‘Synthesis Clock Tree’ window. Click ‘OK’
