asyncvlsi / act Star 120 Code Issues Pull requests ACT hardware description language and core tools. language eda circuit-simulator cad dataflow chp dataflow-programming prs hdl vlsi hardware-description-language production-rules design-automation asynchronous-circuits vlsi-cad asynchronous-vlsi communicating-hardware-processes Updated Nov 1, 2025 C++
broccolimicro / loom Sponsor Star 41 Code Issues Pull requests Discussions design and verification of asynchronous circuits compiler vlsi integrated-circuits hardware-description-language cell-layout asynchronous-circuits electronic-design-automation Updated Oct 4, 2025 Python
asyncvlsi / actflow Star 33 Code Issues Pull requests Top-level repository for the ACT EDA flow asynchronous eda cad vlsi act asynchronous-circuits asynchronous-vlsi self-timed Updated Nov 4, 2025 Shell
tuura / sync-models Star 6 Code Issues Pull requests Tool for creating synchronous models and behavioral specifications for asynchronous circuits verilog model-checking digital-logic formal-verification asynchronous-circuits Updated Jun 19, 2018 Verilog
danielbboy111 / CPEN-311 Star 0 Code Issues Pull requests CPEN 311: Digital Systems Design fpga pipelining mps ic-design combinational-logic asynchronous-circuits gpu-architecture sequential-circuits timing-analysis arithmetic-circuits vhdl-synthesizable datapath-cirucits Updated Mar 12, 2025