CS 254: Assignment 8 Team Members: 1. Devansh Jain (190100044) 2. Harshit Varma (190100055) File Descriptions: Q1: TrafficLightController.vhd : Top-level module that implements a Traffic Light Controller SM1.vhd : State Machine 1 as described in the report SM2.vhd : State Machine 2 as described in the report DFlipFlop.vhd : D-Flipflop using behavioural code NotGate.vhd : NOT Gate using structural modelling AndGate.vhd : AND Gate using structural modelling OrGate.vhd : OR Gate using structural modelling XorGate.vhd : XOR Gate using structural modelling TrafficLightControllerTest.vhd : Testbench waveform.png : Screenshot of the simulation results report.pdf : Report describing the State Machines