A comprehensive UVM (Universal Verification Methodology) testbench for verifying a YAPP (Yet Another Packet Protocol) router. This project demonstrates advanced UVM concepts including verification component (UVC) development, factory pattern implementation, and configuration management.

This project implements a complete UVM verification environment for a packet router using the YAPP protocol. It includes two main tasks that progressively build complexity:

• Task 1: Basic UVC (Universal Verification Component) implementation
• Task 2: Advanced factory pattern and configuration management

├── .gitignore ├── task1_uvc/ │ ├── sv/ │ │ ├── yapp_env.sv │ │ ├── yapp_packet.sv │ │ ├── yapp_pkg.sv │ │ ├── yapp_tx_agent.sv │ │ ├── yapp_tx_driver.sv │ │ ├── yapp_tx_monitor.sv │ │ ├── yapp_tx_seqs.sv │ │ └── yapp_tx_sequencer.sv │ └── tb/ │ ├── router_tb.sv │ ├── router_test_lib.sv │ ├── top.sv │ ├── file.f │ └── run.sh └── task2_factory/ ├── sv/ └── tb/ 

• Address: 2-bit destination address (0, 1, 2)
• Length: 6-bit payload length (1–63 bytes)
• Payload: Variable-length data array
• Parity: 8-bit parity for error detection
• Packet Delay: Configurable transmission delay

• Transaction item class with randomization constraints
• Built-in parity calculation and validation
• Good/bad parity generation
• Packet delay randomization

• Configurable active/passive agent
• Includes driver, sequencer, and monitor
• Automatic component connection

• Drives transactions to the DUT
• Implements the YAPP protocol
• Transaction logging

• Observes DUT transactions
• Performs protocol checks
• Acts as a coverage point

• Coordinates sequence execution using UVM sequencing mechanism

// Generates 5 random packets for basic testing class yapp_5_packets extends yapp_base_seq; virtual task body(); repeat(5) begin `uvm_do(req) end endtask endclass

// Constrained packet for specific test scenarios class short_yapp_packet extends yapp_packet; constraint packet_length { payload.size() inside {[1:14]}; } constraint exclude_address { addr != 2; } endclass

// Replace default packet with short packet variant set_type_override_by_type( yapp_packet::get_type(), short_yapp_packet::get_type() );

• Cadence Xcelium simulator
• UVM 1.1d or later
• SystemVerilog compiler

cd task1_uvc/tb xrun -f file.f -access +rwc -uvm

cd task2_factory/tb xrun -f file.f -access +rwc -uvm +UVM_TESTNAME=short_packet_test

+UVM_VERBOSITY=UVM_HIGH # High verbosity for debugging +UVM_VERBOSITY=UVM_LOW # Lower verbosity for cleaner output

+UVM_TESTNAME=short_packet_test

• Address Range: 0, 1, 2 (valid ports)
• Payload Length: 1–63 bytes
• Parity Distribution: 5:1 ratio (good:bad)
• Packet Delay: 1–20 time units

• Configurable parity error
• Invalid address testing
• Boundary condition testing

• Address coverage
• Payload length edge cases
• Parity type distribution
• Error condition scenarios

1. Basic connectivity
2. Address routing validation
3. Payload length variation
4. Error handling for bad parity

1. Type override behavior
2. Runtime configuration via config DB
3. Polymorphism with packet variants

# UVM_INFO yapp_tx_driver.sv(28) @ 0: uvm_test_top.env_top.env.agent.driver [yapp_tx_driver] Packet is ------------------------------ Name Type Size Value ------------------------------ req yapp_packet - @534 addr integral 2 'h1 length integral 6 'h8 payload da(integral) 8 - [0] integral 8 'h9a [1] integral 8 'h12 ... 

# UVM_INFO @ 0: reporter [FACTORY] #### Factory Configuration (*) Type Overrides: Requested Type Override Type -------------- ------------- yapp_packet short_yapp_packet 

• Transaction logging via uvm_info
• Phase execution tracking
• Factory override visibility
• Config DB trace support
• Waveform dumping support (-gui flag)