packet-router

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Hithaishisr / Router-1x3

A Verilog RTL design of a 1x3 packet router with a complete UVM testbench for verification. Includes FIFO buffers, FSM control, assertions, coverage, and synthesis support.

coverage fsm assertions verilog vcs synthesis systemverilog hardware-designs fifo vlsi questasim uvm digital-design functional-verification rtl-design uvm-testbench packet-router

Updated Sep 3, 2025
JavaScript

SuggarGrandma420 / Router-1x3

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🚦 Build and verify a 1x3 packet router with modular Verilog RTL and a UVM-based environment for efficient functional testing and coverage.

coverage fsm assertions verilog vcs synthesis systemverilog hardware-designs fifo vlsi questasim uvm digital-design functional-verification rtl-design uvm-testbench packet-router

Updated Nov 18, 2025
JavaScript

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