A High-performance Timing Analysis Tool for VLSI Systems

Standard Cell Library based Memory Compiler using FF/Latch cells

A Reconfigurable RISC-V Core for Approximate Computing

Материалы для курсов по проектированию цифровых вычислительных систем

FAN (fan-out-oriented) ATPG (Automatic Test Pattern Generation) and Fault Simulation command line tool

Atalanta is a modified ATPG (Automatic Test Pattern Generation) tool and fault simulator, orginally from VirginiaTech University.

DATC RDF

Delta Sigma DAC FPGA

Verilog Implementation of 32-bit Floating Point Adder

Dadda multiplier(8*8, 16*16, 32*32) in Verilog HDL.

Efficient FPGA-Based Accelerator for Convolutional Neural Networks

This repository is dedicated to VLSI ASIC Design Flow using open-source tools! Here, we embark on a journey that starts with specifications, RTL DV, Synthesis, Physical Design, Signoff and Finally Tape-It-Out

Submission template for Tiny Tapeout IHP shuttles - Verilog HDL Projects

All the projects and assignments done as part of VLSI course.

This repository contain the implementaton of RV32I 5-Stage-Pipeline-Processor based on RISC-V ISA and designed on Verilog

This repository contains the complete Verilog implementation and supporting tools for a cycle-accurate, dual-issue pipelined multimedia processor inspired by the Synergistic Processing Unit (SPU) of the Cell Broadband Engine architecture.

R22SDF FFT VLSI/FPGA investigate and implementation

Repository for RTL building blocks #100daysofrtl VERILOG VHDL System Verilog

Computer Architecture -VLSI -Verilog Codes-Xilinx-Irsim

Projects and labs from the courses dictated in https://www.coursera.org/specializations/fpga-design. Projects are sometimes simulated, and implemented in either a MAX10-Lite or an Arrow MAX1000 board.-