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systemrdl-compiler

Here are 5 public repositories matching this topic...

SystemRDL / PeakRDL

Control and status register code generator toolchain

asic fpga eda verilog csr command-line-tool systemverilog uvm registers axi amba apb register-descriptions systemrdl-compiler hardware-description-language uvm-register-model

Updated Oct 10, 2025
Python

SystemRDL / PeakRDL-regblock

Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.

asic fpga csr systemverilog registers systemverilog-hdl systemrdl systemrdl-compiler

Updated Oct 14, 2025
Python

SystemRDL / PeakRDL-ipxact

Import and export IP-XACT XML register models

asic fpga eda ip-xact register-descriptions systemrdl-compiler ipxact

Updated Sep 17, 2025
Python

srdl2sv

Silicon1602 / srdl2sv

A SystemRDL 2.0 to (synthesizable) SystemVerilog compiler.

asic fpga verilog rdl systemverilog hdl registers systemrdl systemrdl-compiler hardware-description-language register-description-language

Updated Nov 27, 2021
Python

andjeraj / DEDA_Class_2017

This repository is for DEDA class in 2017.

financial-analysis systemrdl-compiler macro-processor

Updated Aug 15, 2019
Python

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