CNN accelerator implemented with Spinal HDL

[HPCA'21] SpAtten: Efficient Sparse Attention Architecture with Cascade Token and Head Pruning

A reimplementation of a tiny stack CPU

High performance LA32R out-of-order processor core. (NSCSCC 2023 Special Prize)

An High-Performance SLAM Hardware Accelerator Implementation for FPGA

The SpinalHDL design of the Proteus core, an extensible RISC-V core.

SpinalHDL - Cryptography libraries

SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype

shdl6800: A 6800 processor written in SpinalHDL

CNN accelerator implemented with Spinal HDL

A classic 5-stage rv32i(incomplete) toy implementation based on powerful SpinalHDL

A 32-bit CPU being developed in SpinalHDL

Reusable small hardware components for SpinalHDL

Mill template for beginning your SpinalHDL project

FPGA friendly Multiport memories (N-read-M-write) based on LVT

Visual Simulation for SpinalHDL

A collection of side-channel hardening extensions for the hardware description language SpinalHDL

A basic SpinalHDL project, configured with Gradle instead of SBT

whackamole game written in SpinalHDL

An attempt to generate Verilog with parameters using SpinalHDL.