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parameterized

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VLSI-Shubh / UART

Fully parameterized UART (Universal Asynchronous Receiver Transmitter) module in Verilog with FSM-based transmitter and receiver, configurable baud rate generator, and support for full-duplex communication. Includes 16x oversampling for accurate bit sampling and loopback testbench for simulation.

verilog-hdl uart-protocol parameterized fpga-programming rtl-design hardware-design

Updated Aug 15, 2025
Verilog

Hammersamatom / cla

Verilog file for a parameterized Carry Lookahead Adder (CLA), Lookahead Carry Unit and Generate/Propagate are combined

fpga verilog logic-gates parameterized

Updated Oct 13, 2023
Verilog

Hammersamatom / rca

Verilog file for a parameterized Ripple Carry Adder (RCA)

fpga verilog logic-gates parameterized

Updated Oct 14, 2023
Verilog

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