This project is to implement a combination lock on the FPGA board using VHDL language and finite state machine. There are some possible solutions are provided to address the problems including debounce, random number generation and combination check.
vhdl finite-state-machine vivado digital-design debounce-button nexys4 random-numbers combination-lock multi-digits-display
- Updated
Jul 29, 2020 - VHDL