Compact and Efficient RISC-V RV32I[MAFC] emulator
emulator virtual-machine riscv jit-compiler bare-metal risc-v instruction-set-simulator gdbstub elf-parser riscv32 rv32imf riscv-simulator riscv-emulator system-emulation
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Oct 15, 2025 - C
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instruction-set-simulator
Here are 27 public repositories matching this topic...
Instruction set simulator for RISC-V, MIPS and ARM-v6m
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Sep 18, 2021 - C++
HF-RISC SoC
mips processor embedded-systems computer-architecture soc instruction-set-architecture risc-v instruction-set-simulator mpsoc hf-risc
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Sep 19, 2025 - C
Extendable Translating Instruction Set Simulator
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Oct 14, 2025 - C++
Simple instruction set simulator for ARMv6-M (Cortex M0)
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Jun 2, 2019 - C++
Online RISC-V/MIPS Assembler & Simulator
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Jul 18, 2022 - JavaScript
LIME is an emulator of fantasy (digital) machines like those developed by community and non-community projects like fox32, OkamiStation, XrArch, Aphelion, doubleword, etc.
emulator simulator isa instruction-set-architecture instruction-set-simulator low-level-programming instruction-set console-emulator low-level-design computer-simulator
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May 4, 2025 - C
A translator to translate RV32I to REBEL-6. Includes custom assemblers to output RV32I (and hopefully soon REBEL-6) MRCS-readable object files, and assembly level simulators to simulate RV32I and REBEL-6 assembly code execution
riscv balanced-ternary ternary risc-v instruction-set-simulator rv32i cpu-simulator ternary-computer binary-to-ternary rebel-6 rv32i-to-rebel binary-to-ternary-translation instruction-set-translation c-to-ternary-pipeline ternary-computing
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Jun 16, 2025 - C++
C++ Instruction Set Simulator for RISC-V RV32IMC & custom SIMD instructions with cache and branch predictor models, C/ASM workloads, and Python analysis tools
emulator cache simd riscv performance-visualization performance-analysis risc-v instruction-set-simulator cache-simulator baremetal branch-prediction coremark rv32i dhrystone rv32im rv32imc dpi-c branch-predictors embench
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Oct 16, 2025 - C++
Instruction set simulator for a MIPS-like processor, and its GUI in Ruby gtk3
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Jan 15, 2021 - Ruby
An easy-to-use, still-in-development RISC-V 32-bit instruction-accurate (IA) simulator.
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Aug 3, 2024 - C++
A C++ program which emulates the instruction decoding of an Intel x86 32-bit processor, with the ability to easily add non-implemented instructions.
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Aug 2, 2025 - C++
Sngle-cycle, Multi-cycle and Pipeline MIPS implementations; Spring 2022
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Jul 3, 2023 - Verilog
A simulator for RISC-V instruction sets
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Oct 10, 2018 - Java
Assembly Learning Environment for Kids
assembly assembly-language machine-code instruction-set-simulator color-codes machine-language kids-learning-app kids-programming character-codes assembly-language-learning
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Apr 7, 2023 - Python
The Project aims to develop a Fast instruction set simulator for Infinion tricore ISA to emulate an actual ECU for car manufacturing industry.
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Feb 23, 2023 - C++
C++ basic instruction set simulator
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Nov 5, 2023 - C++
Simulator foundry for RISC-V ISA - early stage
decompiler riscv isa risc-v instruction-set-simulator instruction-set riscv-simulator riscv-emulator
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Nov 30, 2020 - C++
RAM emulator utilizing C++ language modification that utilizes a preprocessor allowing you to use Random Access Machine instructions in C++ which essentially makes it a RAM emulator...
c emulator fast lightweight simulator ram cpp preprocessor low-level domain-specific-language instruction-set-simulator random-access-machine computability ram-machine simple-to-use instruction-set-emulation
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Sep 18, 2024 - C++
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