SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!

Python classes to create agnostic wave files for HDL simulator viewer

Utilities for working with Verilog within Bazel.

Getting started with cocotb

Use GPT-4 to generate, simulate, and visualize Verilog modules from natural language prompts.

This repo allows for GTKWave to parse RISCV-32I from a waveform.