Design Verification of Flash, UART, and SDRAM controller for a 32 bit embedded RISC microprocessor using cocotb.
Basic UVM Testbench to verify AXI stream spec design. Added a wishbone BFM to mimic Wishbone design.
Implementation and structured verification of the ALU ensure that the design meets all functional requirements by effectively supporting both arithmetic and logical operations, incorporating comprehensive status flag management, and following a rigorous verification methodology
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