DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow video controller with alpha-blended layers. Docs & TBs included.
- Updated
Apr 8, 2024 - SystemVerilog
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ddr3
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An attempt at making a 2-way superscalar out-of-order riscv processor for an Arty s25 fpga.
processor-architecture fpga processor out-of-order superscalar risc-v processor-simulator ddr3 processor-design axi4 superscalar-cpu
- Updated
Oct 7, 2024 - SystemVerilog
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