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sparkfun
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MicroMod_Teensy_Processor
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Commits on Apr 18, 2022
Create LICENSE.md
nseidle
committed
51ca16d
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Commits on Nov 3, 2021
Correct swapped pin numbers on DAT2/3.
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nseidle
committed
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Commits on Sep 21, 2021
Adding lockable version of PCB
nseidle
committed
46b4240
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Commits on Jul 2, 2021
Fix bad links in readme
nseidle
authored
78651dd
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Commits on Apr 19, 2021
Add beveled edge note to instructions
nseidle
committed
10344c4
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Re-add v15 panel files
nseidle
committed
ab9881e
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Add panel files for v15 with ENIG finish notes
nseidle
committed
1efcfdd
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Add ENIG finish note.
nseidle
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Commits on Oct 19, 2020
Add designed by text on PCB
nseidle
committed
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Create README
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SFEMark
authored
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Commits on Oct 1, 2020
Merge pull request #2 from sparkfun/v15
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nseidle
authored
70cc872
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Update SPI0 net names.
Nathan Seidle
committed
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Commits on Aug 31, 2020
Update MicroMod-Teensy-Panel.brd
Nathan Seidle
committed
7790d6b
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Move trace away from edge to pass DFM requirements
Nathan Seidle
committed
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Commits on Aug 29, 2020
Move trace away from top edge
nseidle
committed
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Commits on Aug 28, 2020
Merge pull request #1 from sparkfun/v15
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nseidle
authored
16a1df5
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Adding production panel files
Nathan Seidle
committed
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Commits on Aug 27, 2020
DFM changes: move traces to avoid t/b stop exposure
Nathan Seidle
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Commits on Aug 26, 2020
Incorporate TP changes
nseidle
committed
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Merge branch 'master' of https://github.com/sparkfun/MicroMod_Teensy_Processor
nseidle
committed
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Production v14 panel and gerber files
nseidle
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581bd61
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moved some TP's around to get clearence for pogopins
Eric Orosel
committed
bfd8660
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Commits on Aug 25, 2020
Connect 3.3V_Controlled to peripherals. Increase internal power trace widths.
Nathan Seidle
committed
7715a54
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Moved test-points for ideal testing
Eric Orosel
committed
1716a6a
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Commits on Aug 24, 2020
Opening layer 2 for better GND connections
nseidle
committed
29b84ea
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High freq trace length matching
nseidle
committed
2b4799a
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Increase TP size and relocate to more open areas
nseidle
committed
7917b07
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Switch layers 2/15 to put ground under xtals. Increase GND plane on layer 15.
nseidle
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50b39e0
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Commits on Aug 21, 2020
Remove traces from beneath xtals.
nseidle
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Commits on Jun 23, 2020
Update copper to v13. Add production files.
Nathan Seidle
committed
5b39f46
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Commits on Jun 19, 2020
Fix incorrect SDA/SCL1 board edge connector pinout
nseidle
committed
2a06ce3
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Fix DAT2/DAT3, now correctly connected to B0_04 and B0_05.
nseidle
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Commits on Jun 9, 2020
Add PROD_IDs to 120ohm ferrite
Nathan Seidle
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Delete MicroMod-Teensy-Testpoint Locations.pdf
Nathan Seidle
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Commits on May 19, 2020
v12 production files
nseidle
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Nathan Seidle