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sifive
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fpga-shells
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terpstra
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Commits on Aug 11, 2020
Merge pull request #142 from sifive/add-ci
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CI: add a scala compilation check
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wit-manifest: bump for newest api-generator-sifive
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wit-manifest: bump sifive-blocks to newest version
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Commits on Aug 10, 2020
wit-manifest: remove dependency on firrtl+chisel+api-scala-sifive
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wit-manifest: depend on current rocket-chip
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Commits on Jul 27, 2020
SDIO: chisel3 <> can't decide connection direction (#141)
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Commits on Jul 22, 2020
xdma: support BARs with physical address != PCIe address (#139)
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Commits on May 5, 2020
Merge pull request #127 from sifive/two-jtag-shells
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VCU118: beautify the code a bit
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Commits on Apr 13, 2020
ethernet: clarify which kind of resets are used (#123)
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Commits on Dec 11, 2019
Ethernet: fix this Overlay
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Commits on Dec 2, 2018
Merge pull request #49 from sifive/dma-ecam-base
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xdma: support ECAM at non-4G boundaries
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vivado tcl: don't fail to run post-impl debug
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Commits on Nov 28, 2018
Merge pull request #48 from sifive/10g-ether
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Commits on Nov 23, 2018
nfmac10g: fix a power-0 bug
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nfmac10g: work around 'byte' keyword conflict
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xxv_ethernet: clean up parameters
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ethernet: fix clock of tx/rx-enable
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ethernet: tie a few choice status pins and allow packet sizes
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ethernet: close timing
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ethernet: split mac/pcs between design/shell
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ethernet: connect the clocks!
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ethernet: a bit more visibility into reset
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ethernet: add QSFP2 as well
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ethernet: supply a legit dclk
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xxv_ethernet: assign pins => no need for location/group
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ethernet: compiles to verilog
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xxv_ethernet: add support for 10G transceiver
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Commits on Oct 14, 2018
mbus: switch to multi-bank API (#44)
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Commits on Aug 27, 2018
VC707Shell: default to 1GB of RAM (what the board ships with) (#40)
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Commits on Aug 10, 2018
vcu118: make it possible to instantiate two PCIe interfaces at once (#36)
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Merge pull request #35 from sifive/vcu118-pcie
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Commits on Aug 9, 2018
xilinx: factor out pllReset better
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