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asm! should actually understand "can you address this register?" #126890

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asm! should actually understand "can you address this register?"#126890
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A-inline-assemblyArea: Inline assembly (`asm!(…)`)C-cleanupCategory: PRs that clean code up or issues documenting cleanup.O-AArch64Armv8-A or later processors in AArch64 modeO-riscvTarget: RISC-V architectureT-compilerRelevant to the compiler team, which will review and decide on the PR/issue.T-libsRelevant to the library team, which will review and decide on the PR/issue.
@workingjubilee

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@workingjubilee
workingjubilee
opened on Jun 24, 2024

In #126849 I fixed a bug on 32-bit Arm regarding features that govern "which register fits where" by sorting the features based on register class hierarchically.

However, this bug is present on more than 32-bit Arm:

rust/compiler/rustc_target/src/asm/aarch64.rs

Lines 134 to 149 in 0d8f734

v0: vreg, vreg_low16 = ["v0", "b0", "h0", "s0", "d0", "q0", "z0"],
v1: vreg, vreg_low16 = ["v1", "b1", "h1", "s1", "d1", "q1", "z1"],
v2: vreg, vreg_low16 = ["v2", "b2", "h2", "s2", "d2", "q2", "z2"],
v3: vreg, vreg_low16 = ["v3", "b3", "h3", "s3", "d3", "q3", "z3"],
v4: vreg, vreg_low16 = ["v4", "b4", "h4", "s4", "d4", "q4", "z4"],
v5: vreg, vreg_low16 = ["v5", "b5", "h5", "s5", "d5", "q5", "z5"],
v6: vreg, vreg_low16 = ["v6", "b6", "h6", "s6", "d6", "q6", "z6"],
v7: vreg, vreg_low16 = ["v7", "b7", "h7", "s7", "d7", "q7", "z7"],
v8: vreg, vreg_low16 = ["v8", "b8", "h8", "s8", "d8", "q8", "z8"],
v9: vreg, vreg_low16 = ["v9", "b9", "h9", "s9", "d9", "q9", "z9"],
v10: vreg, vreg_low16 = ["v10", "b10", "h10", "s10", "d10", "q10", "z10"],
v11: vreg, vreg_low16 = ["v11", "b11", "h11", "s11", "d11", "q11", "z11"],
v12: vreg, vreg_low16 = ["v12", "b12", "h12", "s12", "d12", "q12", "z12"],
v13: vreg, vreg_low16 = ["v13", "b13", "h13", "s13", "d13", "q13", "z13"],
v14: vreg, vreg_low16 = ["v14", "b14", "h14", "s14", "d14", "q14", "z14"],
v15: vreg, vreg_low16 = ["v15", "b15", "h15", "s15", "d15", "q15", "z15"],

In addition, there's some very ad-hoc restrictions showing up that in many cases are basically trying to encode the same thing:

rust/compiler/rustc_target/src/asm/riscv.rs

Lines 81 to 96 in 0d8f734

x16: reg = ["x16", "a6"] % not_e,
x17: reg = ["x17", "a7"] % not_e,
x18: reg = ["x18", "s2"] % not_e,
x19: reg = ["x19", "s3"] % not_e,
x20: reg = ["x20", "s4"] % not_e,
x21: reg = ["x21", "s5"] % not_e,
x22: reg = ["x22", "s6"] % not_e,
x23: reg = ["x23", "s7"] % not_e,
x24: reg = ["x24", "s8"] % not_e,
x25: reg = ["x25", "s9"] % not_e,
x26: reg = ["x26", "s10"] % not_e,
x27: reg = ["x27", "s11"] % not_e,
x28: reg = ["x28", "t3"] % not_e,
x29: reg = ["x29", "t4"] % not_e,
x30: reg = ["x30", "t5"] % not_e,
x31: reg = ["x31", "t6"] % not_e,

I believe we should switch to modeling register addressability more directly, and test more exhaustively for all architectural variations people want us to support.

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    A-inline-assemblyArea: Inline assembly (`asm!(…)`)C-cleanupCategory: PRs that clean code up or issues documenting cleanup.O-AArch64Armv8-A or later processors in AArch64 modeO-riscvTarget: RISC-V architectureT-compilerRelevant to the compiler team, which will review and decide on the PR/issue.T-libsRelevant to the library team, which will review and decide on the PR/issue.

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