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14 changes: 0 additions & 14 deletions src/shims/aarch64.rs
Original file line number Diff line number Diff line change
Expand Up @@ -19,20 +19,6 @@ pub(super) trait EvalContextExt<'tcx>: crate::MiriInterpCxExt<'tcx> {
// Prefix should have already been checked.
let unprefixed_name = link_name.as_str().strip_prefix("llvm.aarch64.").unwrap();
match unprefixed_name {
"isb" => {
let [arg] = this.check_shim_sig_lenient(abi, CanonAbi::C, link_name, args)?;
let arg = this.read_scalar(arg)?.to_i32()?;
match arg {
// SY ("full system scope")
15 => {
this.yield_active_thread();
}
_ => {
throw_unsup_format!("unsupported llvm.aarch64.isb argument {}", arg);
}
}
}

// Used to implement the vpmaxq_u8 function.
// Computes the maximum of adjacent pairs; the first half of the output is produced from the
// `left` input, the second half of the output from the `right` input.
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16 changes: 0 additions & 16 deletions src/shims/foreign_items.rs
Original file line number Diff line number Diff line change
Expand Up @@ -813,22 +813,6 @@ trait EvalContextExtPriv<'tcx>: crate::MiriInterpCxExt<'tcx> {
this, link_name, abi, args, dest,
);
}
// FIXME: Move this to an `arm` submodule.
"llvm.arm.hint" if this.tcx.sess.target.arch == Arch::Arm => {
let [arg] = this.check_shim_sig_lenient(abi, CanonAbi::C, link_name, args)?;
let arg = this.read_scalar(arg)?.to_i32()?;
// Note that different arguments might have different target feature requirements.
match arg {
// YIELD
1 => {
this.expect_target_feature_for_intrinsic(link_name, "v6")?;
this.yield_active_thread();
}
_ => {
throw_unsup_format!("unsupported llvm.arm.hint argument {}", arg);
}
}
}

// Fallback to shims in submodules.
_ => {
Expand Down