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Merged
merged 3 commits into from
Jun 11, 2024
Merged

Miscellaneous fixes #175

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1075c4c
Fix SIMDPP_VEC_ARRAY_IMPL_* macros to only use constant expressions
p12tic Jun 11, 2024
d1834c5
Hide GCC-specific warning pragmas on clang
p12tic Jun 11, 2024
6abe1f1
Fix type conversion templates to only use constant expressions
p12tic Jun 11, 2024
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12 changes: 6 additions & 6 deletions simdpp/detail/insn/align.h
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Expand Up @@ -83,7 +83,7 @@ uint8<64> i_align16(const uint8<64>& lower, const uint8<64>& upper)
template<unsigned shift, unsigned N> SIMDPP_INL
uint8<N> i_align16(const uint8<N>& lower, const uint8<N>& upper)
{
SIMDPP_VEC_ARRAY_IMPL2(uint8<N>, i_align16<shift>, lower, upper);
SIMDPP_VEC_ARRAY_IMPL2(uint8<N>, uint8<N>, i_align16<shift>, lower, upper);
}

// -----------------------------------------------------------------------------
Expand Down Expand Up @@ -126,7 +126,7 @@ uint16<32> i_align8(const uint16<32>& lower, const uint16<32>& upper)
template<unsigned shift, unsigned N> SIMDPP_INL
uint16<N> i_align8(const uint16<N>& lower, const uint16<N>& upper)
{
SIMDPP_VEC_ARRAY_IMPL2(uint16<N>, i_align8<shift>, lower, upper);
SIMDPP_VEC_ARRAY_IMPL2(uint16<N>, uint16<N>, i_align8<shift>, lower, upper);
}

// -----------------------------------------------------------------------------
Expand Down Expand Up @@ -203,7 +203,7 @@ uint32<16> i_align4(const uint32<16>& lower, const uint32<16>& upper)
template<unsigned shift, unsigned N> SIMDPP_INL
uint32<N> i_align4(const uint32<N>& lower, const uint32<N>& upper)
{
SIMDPP_VEC_ARRAY_IMPL2(uint32<N>, i_align4<shift>, lower, upper);
SIMDPP_VEC_ARRAY_IMPL2(uint32<N>, uint32<N>, i_align4<shift>, lower, upper);
}

// -----------------------------------------------------------------------------
Expand Down Expand Up @@ -269,7 +269,7 @@ uint64<8> i_align2(const uint64<8>& lower, const uint64<8>& upper)
template<unsigned shift, unsigned N> SIMDPP_INL
uint64<N> i_align2(const uint64<N>& lower, const uint64<N>& upper)
{
SIMDPP_VEC_ARRAY_IMPL2(uint64<N>, i_align2<shift>, lower, upper);
SIMDPP_VEC_ARRAY_IMPL2(uint64<N>, uint64<N>, i_align2<shift>, lower, upper);
}

// -----------------------------------------------------------------------------
Expand Down Expand Up @@ -365,7 +365,7 @@ float32<16> i_align4(const float32<16>& lower, const float32<16>& upper)
template<unsigned shift, unsigned N> SIMDPP_INL
float32<N> i_align4(const float32<N>& lower, const float32<N>& upper)
{
SIMDPP_VEC_ARRAY_IMPL2(float32<N>, i_align4<shift>, lower, upper);
SIMDPP_VEC_ARRAY_IMPL2(float32<N>, float32<N>, i_align4<shift>, lower, upper);
}

// -----------------------------------------------------------------------------
Expand Down Expand Up @@ -439,7 +439,7 @@ float64<8> i_align2(const float64<8>& lower, const float64<8>& upper)
template<unsigned shift, unsigned N> SIMDPP_INL
float64<N> i_align2(const float64<N>& lower, const float64<N>& upper)
{
SIMDPP_VEC_ARRAY_IMPL2(float64<N>, i_align2<shift>, lower, upper);
SIMDPP_VEC_ARRAY_IMPL2(float64<N>, float64<N>, i_align2<shift>, lower, upper);
}

} // namespace insn
Expand Down
2 changes: 1 addition & 1 deletion simdpp/detail/insn/bit_and.h
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Expand Up @@ -617,7 +617,7 @@ mask_float64<8> i_bit_and(const mask_float64<8>& a, const mask_float64<8>& b)
template<class V, class VM> SIMDPP_INL
V i_bit_and(const V& a, const VM& b)
{
SIMDPP_VEC_ARRAY_IMPL2(V, i_bit_and, a, b)
SIMDPP_VEC_ARRAY_IMPL2(V, V, i_bit_and, a, b)
}

} // namespace insn
Expand Down
2 changes: 1 addition & 1 deletion simdpp/detail/insn/bit_andnot.h
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Expand Up @@ -617,7 +617,7 @@ mask_float64<8> i_bit_andnot(const mask_float64<8>& a, const mask_float64<8>& b)
template<class V, class VM> SIMDPP_INL
V i_bit_andnot(const V& a, const VM& b)
{
SIMDPP_VEC_ARRAY_IMPL2(V, i_bit_andnot, a, b)
SIMDPP_VEC_ARRAY_IMPL2(V, V, i_bit_andnot, a, b)
}

} // namespace insn
Expand Down
2 changes: 1 addition & 1 deletion simdpp/detail/insn/bit_not.h
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Expand Up @@ -351,7 +351,7 @@ mask_float64<8> i_bit_not(const mask_float64<8>& a)
template<class V> SIMDPP_INL
V i_bit_not(const V& a)
{
SIMDPP_VEC_ARRAY_IMPL1(V, i_bit_not, a)
SIMDPP_VEC_ARRAY_IMPL1(V, V, i_bit_not, a)
}

} // namespace insn
Expand Down
2 changes: 1 addition & 1 deletion simdpp/detail/insn/bit_or.h
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Expand Up @@ -415,7 +415,7 @@ mask_float64<8> i_bit_or(const mask_float64<8>& a, const mask_float64<8>& b)
template<class V, class VM> SIMDPP_INL
V i_bit_or(const V& a, const VM& b)
{
SIMDPP_VEC_ARRAY_IMPL2(V, i_bit_or, a, b)
SIMDPP_VEC_ARRAY_IMPL2(V, V, i_bit_or, a, b)
}

} // namespace insn
Expand Down
2 changes: 1 addition & 1 deletion simdpp/detail/insn/bit_select.h
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Expand Up @@ -697,7 +697,7 @@ static SIMDPP_INL
template<class V1, class V2, class V3> SIMDPP_INL
V1 i_bit_select(const V1& on, const V2& off, const V3& mask)
{
SIMDPP_VEC_ARRAY_IMPL3(V1, i_bit_select, on, off, mask)
SIMDPP_VEC_ARRAY_IMPL3(V1, V1, i_bit_select, on, off, mask)
}


Expand Down
2 changes: 1 addition & 1 deletion simdpp/detail/insn/bit_xor.h
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Expand Up @@ -418,7 +418,7 @@ mask_float64<8> i_bit_xor(const mask_float64<8>& a, const mask_float64<8>& b)
template<class V, class VM> SIMDPP_INL
V i_bit_xor(const V& a, const VM& b)
{
SIMDPP_VEC_ARRAY_IMPL2(V, i_bit_xor, a, b)
SIMDPP_VEC_ARRAY_IMPL2(V, V, i_bit_xor, a, b)
}

} // namespace insn
Expand Down
2 changes: 1 addition & 1 deletion simdpp/detail/insn/blend.h
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Expand Up @@ -666,7 +666,7 @@ mask_float64<8> i_blend(const mask_float64<8>& on, const mask_float64<8>& off, c
template<class V1, class V2, class V3> SIMDPP_INL
V1 i_blend(const V1& on, const V2& off, const V3& mask)
{
SIMDPP_VEC_ARRAY_IMPL3(V1, i_blend, on, off, mask)
SIMDPP_VEC_ARRAY_IMPL3(V1, V1, i_blend, on, off, mask)
}


Expand Down
2 changes: 1 addition & 1 deletion simdpp/detail/insn/cmp_eq.h
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Expand Up @@ -405,7 +405,7 @@ mask_float64<8> i_cmp_eq(const mask_float64<8>& a, const mask_float64<8>& b)
template<class V> SIMDPP_INL
typename V::mask_vector_type i_cmp_eq(const V& a, const V& b)
{
SIMDPP_VEC_ARRAY_IMPL2(typename V::mask_vector_type, i_cmp_eq, a, b);
SIMDPP_VEC_ARRAY_IMPL2(typename V::mask_vector_type, V, i_cmp_eq, a, b);
}

} // namespace insn
Expand Down
2 changes: 1 addition & 1 deletion simdpp/detail/insn/cmp_ge.h
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Expand Up @@ -406,7 +406,7 @@ mask_float64<8> i_cmp_ge(const float64<8>& a, const float64<8>& b)
template<class V> SIMDPP_INL
typename V::mask_vector_type i_cmp_ge(const V& a, const V& b)
{
SIMDPP_VEC_ARRAY_IMPL2(typename V::mask_vector_type, i_cmp_ge, a, b);
SIMDPP_VEC_ARRAY_IMPL2(typename V::mask_vector_type, V, i_cmp_ge, a, b);
}

} // namespace insn
Expand Down
2 changes: 1 addition & 1 deletion simdpp/detail/insn/cmp_gt.h
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Expand Up @@ -469,7 +469,7 @@ mask_float64<8> i_cmp_gt(const float64<8>& a, const float64<8>& b)
template<class V> SIMDPP_INL
typename V::mask_vector_type i_cmp_gt(const V& a, const V& b)
{
SIMDPP_VEC_ARRAY_IMPL2(typename V::mask_vector_type, i_cmp_gt, a, b);
SIMDPP_VEC_ARRAY_IMPL2(typename V::mask_vector_type, V, i_cmp_gt, a, b);
}

} // namespace insn
Expand Down
2 changes: 1 addition & 1 deletion simdpp/detail/insn/cmp_le.h
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Expand Up @@ -405,7 +405,7 @@ mask_float64<8> i_cmp_le(const float64<8>& a, const float64<8>& b)
template<class V> SIMDPP_INL
typename V::mask_vector_type i_cmp_le(const V& a, const V& b)
{
SIMDPP_VEC_ARRAY_IMPL2(typename V::mask_vector_type, i_cmp_le, a, b);
SIMDPP_VEC_ARRAY_IMPL2(typename V::mask_vector_type, V, i_cmp_le, a, b);
}


Expand Down
2 changes: 1 addition & 1 deletion simdpp/detail/insn/cmp_lt.h
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Expand Up @@ -465,7 +465,7 @@ mask_float64<8> i_cmp_lt(const float64<8>& a, const float64<8>& b)
template<class V> SIMDPP_INL
typename V::mask_vector_type i_cmp_lt(const V& a, const V& b)
{
SIMDPP_VEC_ARRAY_IMPL2(typename V::mask_vector_type, i_cmp_lt, a, b);
SIMDPP_VEC_ARRAY_IMPL2(typename V::mask_vector_type, V, i_cmp_lt, a, b);
}

} // namespace insn
Expand Down
2 changes: 1 addition & 1 deletion simdpp/detail/insn/cmp_neq.h
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Expand Up @@ -372,7 +372,7 @@ mask_float64<8> i_cmp_neq(const mask_float64<8>& a, const mask_float64<8>& b)
template<class V> SIMDPP_INL
typename V::mask_vector_type i_cmp_neq(const V& a, const V& b)
{
SIMDPP_VEC_ARRAY_IMPL2(typename V::mask_vector_type, i_cmp_neq, a, b);
SIMDPP_VEC_ARRAY_IMPL2(typename V::mask_vector_type, V, i_cmp_neq, a, b);
}

} // namespace insn
Expand Down
6 changes: 3 additions & 3 deletions simdpp/detail/insn/conv_any_to_float64.h
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Expand Up @@ -128,7 +128,7 @@ template<unsigned N> SIMDPP_INL
float64<N> i_to_float64(const float32<N>& a)
{
float64<N> r;
float32_to_float64_converter<0, a.vec_length, a.base_length, N>::convert(r, a);
float32_to_float64_converter<0, float32<N>::vec_length, float32<N>::base_length, N>::convert(r, a);
return r;
}

Expand Down Expand Up @@ -238,7 +238,7 @@ template<unsigned N> SIMDPP_INL
float64<N> i_to_float64(const int32<N>& a)
{
float64<N> r;
int32_to_float64_converter<0, a.vec_length, a.base_length, N>::convert(r, a);
int32_to_float64_converter<0, int32<N>::vec_length, int32<N>::base_length, N>::convert(r, a);
return r;
}

Expand Down Expand Up @@ -362,7 +362,7 @@ template<unsigned N> SIMDPP_INL
float64<N> i_to_float64(const uint32<N>& a)
{
float64<N> r;
uint32_to_float64_converter<0, a.vec_length, a.base_length, N>::convert(r, a);
uint32_to_float64_converter<0, uint32<N>::vec_length, uint32<N>::base_length, N>::convert(r, a);
return r;
}

Expand Down
4 changes: 2 additions & 2 deletions simdpp/detail/insn/conv_extend_to_int16.h
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Expand Up @@ -111,7 +111,7 @@ template<unsigned N> SIMDPP_INL
uint16<N> i_to_uint16(const uint8<N>& a)
{
uint16<N> r;
uint_8_to_uint16_converter<0, a.vec_length, a.base_length, N>::convert(r, a);
uint_8_to_uint16_converter<0, uint8<N>::vec_length, uint8<N>::base_length, N>::convert(r, a);
return r;
}

Expand Down Expand Up @@ -212,7 +212,7 @@ template<unsigned N> SIMDPP_INL
int16<N> i_to_int16(const int8<N>& a)
{
int16<N> r;
int8_to_int16_converter<0, a.vec_length, a.base_length, N>::convert(r, a);
int8_to_int16_converter<0, int8<N>::vec_length, int8<N>::base_length, N>::convert(r, a);
return r;
}

Expand Down
8 changes: 4 additions & 4 deletions simdpp/detail/insn/conv_extend_to_int32.h
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Expand Up @@ -121,7 +121,7 @@ template<unsigned N> SIMDPP_INL
uint32<N> i_to_uint32(const uint16<N>& a)
{
uint32<N> r;
uint_16_to_uint32_converter<0, a.vec_length, a.base_length, N>::convert(r, a);
uint_16_to_uint32_converter<0, uint16<N>::vec_length, uint16<N>::base_length, N>::convert(r, a);
return r;
}

Expand Down Expand Up @@ -231,7 +231,7 @@ template<unsigned N> SIMDPP_INL
uint32<N> i_to_uint32(const uint8<N>& a)
{
uint32<N> r;
uint_8_to_uint32_converter<0, a.vec_length, a.base_length, N>::convert(r, a);
uint_8_to_uint32_converter<0, uint8<N>::vec_length, uint8<N>::base_length, N>::convert(r, a);
return r;
}

Expand Down Expand Up @@ -330,7 +330,7 @@ template<unsigned N> SIMDPP_INL
int32<N> i_to_int32(const int16<N>& a)
{
int32<N> r;
int16_to_int32_converter<0, a.vec_length, a.base_length, N>::convert(r, a);
int16_to_int32_converter<0, int16<N>::vec_length, int16<N>::base_length, N>::convert(r, a);
return r;
}

Expand Down Expand Up @@ -441,7 +441,7 @@ template<unsigned N> SIMDPP_INL
int32<N> i_to_int32(const int8<N>& a)
{
int32<N> r;
int8_to_int32_converter<0, a.vec_length, a.base_length, N>::convert(r, a);
int8_to_int32_converter<0, int8<N>::vec_length, int8<N>::base_length, N>::convert(r, a);
return r;
}

Expand Down
12 changes: 6 additions & 6 deletions simdpp/detail/insn/conv_extend_to_int64.h
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Expand Up @@ -114,7 +114,7 @@ template<unsigned N> SIMDPP_INL
uint64<N> i_to_uint64(const uint32<N>& a)
{
uint64<N> r;
uint_32_to_uint64_converter<0, a.vec_length, a.base_length, N>::convert(r, a);
uint_32_to_uint64_converter<0, uint32<N>::vec_length, uint32<N>::base_length, N>::convert(r, a);
return r;
}

Expand Down Expand Up @@ -231,7 +231,7 @@ template<unsigned N> SIMDPP_INL
uint64<N> i_to_uint64(const uint16<N>& a)
{
uint64<N> r;
uint_16_to_uint64_converter<0, a.vec_length, a.base_length, N>::convert(r, a);
uint_16_to_uint64_converter<0, uint16<N>::vec_length, uint16<N>::base_length, N>::convert(r, a);
return r;
}

Expand Down Expand Up @@ -370,7 +370,7 @@ template<unsigned N> SIMDPP_INL
uint64<N> i_to_uint64(const uint8<N>& a)
{
uint64<N> r;
uint_8_to_uint64_converter<0, a.vec_length, a.base_length, N>::convert(r, a);
uint_8_to_uint64_converter<0, uint8<N>::vec_length, uint8<N>::base_length, N>::convert(r, a);
return r;
}

Expand Down Expand Up @@ -465,7 +465,7 @@ template<unsigned N> SIMDPP_INL
int64<N> i_to_int64(const int32<N>& a)
{
int64<N> r;
int32_to_int64_converter<0, a.vec_length, a.base_length, N>::convert(r, a);
int32_to_int64_converter<0, int32<N>::vec_length, int32<N>::base_length, N>::convert(r, a);
return r;
}

Expand Down Expand Up @@ -582,7 +582,7 @@ template<unsigned N> SIMDPP_INL
int64<N> i_to_int64(const int16<N>& a)
{
int64<N> r;
int16_to_int64_converter<0, a.vec_length, a.base_length, N>::convert(r, a);
int16_to_int64_converter<0, int16<N>::vec_length, int16<N>::base_length, N>::convert(r, a);
return r;
}

Expand Down Expand Up @@ -721,7 +721,7 @@ template<unsigned N> SIMDPP_INL
int64<N> i_to_int64(const int8<N>& a)
{
int64<N> r;
int8_to_int64_converter<0, a.vec_length, a.base_length, N>::convert(r, a);
int8_to_int64_converter<0, int8<N>::vec_length, int8<N>::base_length, N>::convert(r, a);
return r;
}

Expand Down
4 changes: 2 additions & 2 deletions simdpp/detail/insn/conv_float_to_int32.h
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Expand Up @@ -105,7 +105,7 @@ template<unsigned N> SIMDPP_INL
int32<N> i_to_int32(const float32<N>& a)
{
int32<N> r;
float32_to_int32_converter<0, a.vec_length, a.base_length, N>::convert(r, a);
float32_to_int32_converter<0, float32<N>::vec_length, float32<N>::base_length, N>::convert(r, a);
return r;
}

Expand Down Expand Up @@ -204,7 +204,7 @@ template<unsigned N> SIMDPP_INL
uint32<N> i_to_uint32(const float32<N>& a)
{
uint32<N> r;
float32_to_uint32_converter<0, a.vec_length, a.base_length, N>::convert(r, a);
float32_to_uint32_converter<0, float32<N>::vec_length, float32<N>::base_length, N>::convert(r, a);
return r;
}

Expand Down
8 changes: 4 additions & 4 deletions simdpp/detail/insn/conv_float_to_int64.h
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Expand Up @@ -105,7 +105,7 @@ template<unsigned N> SIMDPP_INL
uint64<N> i_to_uint64(const float64<N>& a)
{
uint64<N> r;
float64_to_uint64_converter<0, a.vec_length, a.base_length, N>::convert(r, a);
float64_to_uint64_converter<0, float64<N>::vec_length, float64<N>::base_length, N>::convert(r, a);
return r;
}

Expand Down Expand Up @@ -195,7 +195,7 @@ template<unsigned N> SIMDPP_INL
int64<N> i_to_int64(const float64<N>& a)
{
int64<N> r;
float64_to_int64_converter<0, a.vec_length, a.base_length, N>::convert(r, a);
float64_to_int64_converter<0, float64<N>::vec_length, float64<N>::base_length, N>::convert(r, a);
return r;
}

Expand Down Expand Up @@ -289,7 +289,7 @@ template<unsigned N> SIMDPP_INL
uint64<N> i_to_uint64(const float32<N>& a)
{
uint64<N> r;
float32_to_uint64_converter<0, a.vec_length, a.base_length, N>::convert(r, a);
float32_to_uint64_converter<0, float32<N>::vec_length, float32<N>::base_length, N>::convert(r, a);
return r;
}

Expand Down Expand Up @@ -384,7 +384,7 @@ template<unsigned N> SIMDPP_INL
int64<N> i_to_int64(const float32<N>& a)
{
int64<N> r;
float32_to_int64_converter<0, a.vec_length, a.base_length, N>::convert(r, a);
float32_to_int64_converter<0, float32<N>::vec_length, float32<N>::base_length, N>::convert(r, a);
return r;
}

Expand Down
2 changes: 1 addition & 1 deletion simdpp/detail/insn/conv_to_mask.inl
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Expand Up @@ -231,7 +231,7 @@ mask_float64<8> i_to_mask(const float64<8>& a)
template<class V> SIMDPP_INL
typename V::mask_vector_type i_to_mask(const V& a)
{
SIMDPP_VEC_ARRAY_IMPL1(typename V::mask_vector_type, i_to_mask, a)
SIMDPP_VEC_ARRAY_IMPL1(typename V::mask_vector_type, V, i_to_mask, a)
}

} // namespace insn
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2 changes: 1 addition & 1 deletion simdpp/detail/insn/f_abs.h
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Expand Up @@ -91,7 +91,7 @@ float64<8> i_fabs(const float64<8>& a)
template<class V> SIMDPP_INL
V i_fabs(const V& a)
{
SIMDPP_VEC_ARRAY_IMPL1(V, i_fabs, a)
SIMDPP_VEC_ARRAY_IMPL1(V, V, i_fabs, a)
}

} // namespace insn
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2 changes: 1 addition & 1 deletion simdpp/detail/insn/f_add.h
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Expand Up @@ -92,7 +92,7 @@ float64<8> i_fadd(const float64<8>& a, const float64<8>& b)
template<class V> SIMDPP_INL
V i_fadd(const V& a, const V& b)
{
SIMDPP_VEC_ARRAY_IMPL2(V, i_fadd, a, b)
SIMDPP_VEC_ARRAY_IMPL2(V, V, i_fadd, a, b)
}

} // namespace insn
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2 changes: 1 addition & 1 deletion simdpp/detail/insn/f_ceil.h
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Expand Up @@ -160,7 +160,7 @@ float64<8> i_ceil(const float64<8>& a)
template<class V> SIMDPP_INL
V i_ceil(const V& a)
{
SIMDPP_VEC_ARRAY_IMPL1(V, i_ceil, a);
SIMDPP_VEC_ARRAY_IMPL1(V, V, i_ceil, a);
}

} // namespace insn
Expand Down
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