[AMX][NFC] Organize tilerow

[mahesh-attarde]

Organizing tilerow for an extension.

[llvmbot]

@llvm/pr-subscribers-mlgo

@llvm/pr-subscribers-backend-x86

Author: Mahesh-Attarde (mahesh-attarde)

Changes

Organizing tilerow for an extension.

---

Full diff: https://github.com/llvm/llvm-project/pull/168193.diff

5 Files Affected:

• (modified) llvm/lib/Target/X86/X86ExpandPseudo.cpp (+2-2)
• (modified) llvm/lib/Target/X86/X86ISelLowering.cpp (+2-2)
• (modified) llvm/lib/Target/X86/X86InstrAMX.td (+8-8)
• (modified) llvm/test/CodeGen/MIR2Vec/Inputs/reference_x86_vocab_print.txt (+2-2)
• (modified) llvm/test/tools/llvm-ir2vec/output/reference_x86_entities.txt (+2-2)

diff --git a/llvm/lib/Target/X86/X86ExpandPseudo.cpp b/llvm/lib/Target/X86/X86ExpandPseudo.cpp index e3c44c048f7bf..0bccbe7f9c927 100644 --- a/llvm/lib/Target/X86/X86ExpandPseudo.cpp +++ b/llvm/lib/Target/X86/X86ExpandPseudo.cpp @@ -638,10 +638,10 @@ bool X86ExpandPseudo::expandMI(MachineBasicBlock &MBB, Opc = X86::TCVTROWPS2PHLrri; break; case X86::PTILEMOVROWrreV: - Opc = X86::TILEMOVROWrre; + Opc = X86::TILEMOVROWrte; break; case X86::PTILEMOVROWrriV: - Opc = X86::TILEMOVROWrri; + Opc = X86::TILEMOVROWrti; break; default: llvm_unreachable("Unexpected Opcode"); diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index a2f505b9cff8a..7baed10fb7503 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -38246,7 +38246,7 @@ X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI, Opc = X86::TCVTROWPS2PHLrri; break; case X86::PTILEMOVROWrri: - Opc = X86::TILEMOVROWrri; + Opc = X86::TILEMOVROWrti; break; } MachineInstrBuilder MIB = BuildMI(*BB, MI, DL, TII->get(Opc)); @@ -38284,7 +38284,7 @@ X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI, Opc = X86::TCVTROWPS2PHLrre; break; case X86::PTILEMOVROWrre: - Opc = X86::TILEMOVROWrre; + Opc = X86::TILEMOVROWrte; break; } MachineInstrBuilder MIB = BuildMI(*BB, MI, DL, TII->get(Opc)); diff --git a/llvm/lib/Target/X86/X86InstrAMX.td b/llvm/lib/Target/X86/X86InstrAMX.td index 522782abd710f..cd3f1fa012f9c 100644 --- a/llvm/lib/Target/X86/X86InstrAMX.td +++ b/llvm/lib/Target/X86/X86InstrAMX.td @@ -475,22 +475,22 @@ defm TCVTROWPS2PHL : AMXAVX512_BASE<0x6d, 0x77, "tcvtrowps2phl", PD, XD>; defm TCVTROWPS2BF16H : AMXAVX512_BASE<0x6d, 0x07, "tcvtrowps2bf16h", XD, XD>; defm TCVTROWPS2BF16L : AMXAVX512_BASE<0x6d, 0x77, "tcvtrowps2bf16l", XS, XS>; -multiclass m_tilemovrow { +multiclass AMXAVX512_TILEMOVE<bits<8> Opcode1, bits<8> Opcode2, string Opstr> { let Predicates = [HasAMXAVX512, HasAVX10_2, In64BitMode] in { let SchedRW = [WriteSystem] in { - def rri : Ii8<0x7, MRMSrcReg, (outs VR512:$dst), + def rti : Ii8<0x7, MRMSrcReg, (outs VR512:$dst), (ins TILE:$src1, u8imm:$src2), - "tilemovrow\t{$src2, $src1, $dst|$dst, $src1, $src2}", - []>, TA,PD, EVEX, EVEX_V512; - def rre : I<0x4A, MRMSrcReg4VOp3, (outs VR512:$dst), + !strconcat(Opstr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), + []>, TA, PD, EVEX, EVEX_V512; + def rte : I<0x4A, MRMSrcReg4VOp3, (outs VR512:$dst), (ins TILE:$src1, GR32:$src2), - "tilemovrow\t{$src2, $src1, $dst|$dst, $src1, $src2}", - []>, T8,PD, EVEX, VVVV, EVEX_V512; + !strconcat(Opstr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), + []>, T8, PD, EVEX, VVVV, EVEX_V512; } } // HasAMXAVX512, HasAVX10_2, In64BitMode } -defm TILEMOVROW : m_tilemovrow; +defm TILEMOVROW : AMXAVX512_TILEMOVE<0x07, 0x4A, "tilemovrow">; let Predicates = [HasAMXAVX512, HasAVX10_2, In64BitMode] in { let SchedRW = [WriteSystem] in { diff --git a/llvm/test/CodeGen/MIR2Vec/Inputs/reference_x86_vocab_print.txt b/llvm/test/CodeGen/MIR2Vec/Inputs/reference_x86_vocab_print.txt index 8af4277f12c65..7131f7108d486 100644 --- a/llvm/test/CodeGen/MIR2Vec/Inputs/reference_x86_vocab_print.txt +++ b/llvm/test/CodeGen/MIR2Vec/Inputs/reference_x86_vocab_print.txt @@ -1733,8 +1733,8 @@ Key: TILELOADDRST: [ 0.00 0.00 ] Key: TILELOADDRS_EVEX: [ 0.00 0.00 ] Key: TILELOADDT: [ 0.00 0.00 ] Key: TILELOADD_EVEX: [ 0.00 0.00 ] -Key: TILEMOVROWrre: [ 0.00 0.00 ] -Key: TILEMOVROWrri: [ 0.00 0.00 ] +Key: TILEMOVROWrte: [ 0.00 0.00 ] +Key: TILEMOVROWrti: [ 0.00 0.00 ] Key: TILERELEASE: [ 0.00 0.00 ] Key: TILESTORED: [ 0.00 0.00 ] Key: TILESTORED_EVEX: [ 0.00 0.00 ] diff --git a/llvm/test/tools/llvm-ir2vec/output/reference_x86_entities.txt b/llvm/test/tools/llvm-ir2vec/output/reference_x86_entities.txt index 1b90a8a75a80e..ad11e47cc2f83 100644 --- a/llvm/test/tools/llvm-ir2vec/output/reference_x86_entities.txt +++ b/llvm/test/tools/llvm-ir2vec/output/reference_x86_entities.txt @@ -1734,8 +1734,8 @@ TILELOADDRST	1731 TILELOADDRS_EVEX	1732 TILELOADDT	1733 TILELOADD_EVEX	1734 -TILEMOVROWrre	1735 -TILEMOVROWrri	1736 +TILEMOVROWrte	1735 +TILEMOVROWrti	1736 TILERELEASE	1737 TILESTORED	1738 TILESTORED_EVEX	1739 

[phoebewang]

Please change all instructions that have mixed tile and non tile registers.

[phoebewang]

@RKSimon are you happy with using t for tile registers. I recall we discussed somewhere that using different name for GPR and vector registers. Maybe we can start from tile registers since the instructions are small?

[RKSimon]

@RKSimon are you happy with using t for tile registers. I recall we discussed somewhere that using different name for GPR and vector registers. Maybe we can start from tile registers since the instructions are small?

Yes, making it easier to distinguish between the main register types would mean its much easier to dynamically determine the instruction enum names (moves between reg types in particular is a mess). 't' for amx tile registers sounds good to me for starters thank you.