Commits

Commits on Oct 24, 2025

[RISCV] Add LLVM IR intrinsics and codegen for XSfvfexp* and XSfvfexpa* (#164499)

authored

Commits on Oct 22, 2025

[RISCV][MC] Introduce XSfvfexp* and XSfvfbfexpa* extensions and their MC supports (#164349)

authored

Commits on Oct 10, 2025

[RISCV] Toggle throttled FP64 feature in SiFive7 scheduling model with subtarget feature (#162400)
mshockwave
authored
[RISCV] Add a new subtarget feature for throttled FP64 vector performance (#162399)
mshockwave
authored

Commits on Oct 8, 2025

[clang][Driver][RISCV] Rename `getRISCFeaturesFromMcpu`. NFCI (#162545)
mshockwave
authored

Commits on Oct 7, 2025

Commits on Oct 5, 2025

[MachineScheduler] Convert some of the debug prints into using LDBG. NFC (#161997)
mshockwave
authored

Commits on Oct 4, 2025

Commits on Oct 3, 2025

[SelectionDAG] Add support to dump DAGs with sorted nodes (#161097)
mshockwave
authored

Commits on Sep 26, 2025

[RISCV] Update SiFive7's scheduling models with their optimizations on permutation instructions (#160763)

mshockwave
and
michaelmaitland
authored

Commits on Sep 23, 2025

[RISCV] Update SiFive7's scheduling model on mask and data movement instructions (#160155)

mshockwave
and
michaelmaitland
authored

Commits on Sep 18, 2025

Commits on Sep 17, 2025

[RISCV][NFC] Merge some WriteRes entries in SiFive7 scheduling model (#159448)
mshockwave
authored

Commits on Sep 4, 2025

Commits on Sep 2, 2025

Commits on Aug 26, 2025

Commits on Aug 20, 2025

[AMDGPU] Fix uncaught changes made by AMDGPUPreloadKernelArgumentsPass (#154645)
mshockwave
authored

Commits on Aug 19, 2025

[RISCV] Handle more cases when combining (vfmv.s.f (extract_subvector X, 0)) (#154175)

mshockwave
and
topperc
authored

Commits on Aug 15, 2025

Commits on Aug 14, 2025

Commits on Aug 12, 2025

[IA][RISCV] Recognize deinterleaved loads that could lower to strided segmented loads (#151612)
mshockwave
authored

Commits on Aug 8, 2025

Commits on Aug 2, 2025

[DAG] Always use stack to promote bitcast when the source is vector (#151065)
mshockwave
authored

Commits on Aug 1, 2025

[RISCV] Add intrinsics for strided segment loads with fixed vectors (#151611)
mshockwave
authored