AArch64: Use Register in FrameLowering

Author: arsenm

llvm/lib/Target/AArch64/AArch64FrameLowering.cpp

@@ -1589,30 +1589,30 @@ static bool invalidateRegisterPairing(unsigned Reg1, unsigned Reg2,
 namespace {
 
 struct RegPairInfo {
- unsigned Reg1 = AArch64::NoRegister;
- unsigned Reg2 = AArch64::NoRegister;
+ Register Reg1;
+ Register Reg2;
  int FrameIdx;
  int Offset;
  enum RegType { GPR, FPR64, FPR128, PPR, ZPR, VG } Type;
  const TargetRegisterClass *RC;
 
  RegPairInfo() = default;
 
- bool isPaired() const { return Reg2 != AArch64::NoRegister; }
+ bool isPaired() const { return Reg2.isValid(); }
 
  bool isScalable() const { return Type == PPR || Type == ZPR; }
 };
 
 } // end anonymous namespace
 
-unsigned findFreePredicateReg(BitVector &SavedRegs) {
+MCRegister findFreePredicateReg(BitVector &SavedRegs) {
  for (unsigned PReg = AArch64::P8; PReg <= AArch64::P15; ++PReg) {
  if (SavedRegs.test(PReg)) {
  unsigned PNReg = PReg - AArch64::P0 + AArch64::PN0;
- return PNReg;
+ return MCRegister(PNReg);
  }
  }
- return AArch64::NoRegister;
+ return MCRegister();
 }
 
 // The multivector LD/ST are available only for SME or SVE2p1 targets
@@ -1930,8 +1930,8 @@ bool AArch64FrameLowering::spillCalleeSavedRegisters(
  }
  bool PTrueCreated = false;
  for (const RegPairInfo &RPI : llvm::reverse(RegPairs)) {
- unsigned Reg1 = RPI.Reg1;
- unsigned Reg2 = RPI.Reg2;
+ Register Reg1 = RPI.Reg1;
+ Register Reg2 = RPI.Reg2;
  unsigned StrOpc;
 
  // Issue sequence of spills for cs regs. The first spill may be converted
@@ -1967,7 +1967,7 @@ bool AArch64FrameLowering::spillCalleeSavedRegisters(
  break;
  }
 
- unsigned X0Scratch = AArch64::NoRegister;
+ Register X0Scratch;
  auto RestoreX0 = make_scope_exit([&] {
  if (X0Scratch != AArch64::NoRegister)
  BuildMI(MBB, MI, DL, TII.get(TargetOpcode::COPY), AArch64::X0)
@@ -2530,8 +2530,8 @@ void AArch64FrameLowering::determineCalleeSaves(MachineFunction &MF,
  AArch64FunctionInfo *AFI = MF.getInfo<AArch64FunctionInfo>();
  // Find a suitable predicate register for the multi-vector spill/fill
  // instructions.
- unsigned PnReg = findFreePredicateReg(SavedRegs);
- if (PnReg != AArch64::NoRegister)
+ MCRegister PnReg = findFreePredicateReg(SavedRegs);
+ if (PnReg.isValid())
  AFI->setPredicateRegForFillSpill(PnReg);
  // If no free callee-save has been found assign one.
  if (!AFI->getPredicateRegForFillSpill() &&