[AMDGPU][NPM] Port AMDGPUMarkLastScratchLoad to NPM (#131738)

This finishes all passes for the optimized regalloc path. --------- Co-authored-by: Matt Arsenault <Matthew.Arsenault@amd.com>

Author: optimisan

llvm/lib/Target/AMDGPU/AMDGPU.h

@@ -195,7 +195,7 @@ extern char &AMDGPURegBankSelectID;
 void initializeAMDGPURegBankLegalizePass(PassRegistry &);
 extern char &AMDGPURegBankLegalizeID;
 
-void initializeAMDGPUMarkLastScratchLoadPass(PassRegistry &);
+void initializeAMDGPUMarkLastScratchLoadLegacyPass(PassRegistry &);
 extern char &AMDGPUMarkLastScratchLoadID;
 
 void initializeSILowerSGPRSpillsLegacyPass(PassRegistry &);
@@ -371,6 +371,13 @@ class GCNCreateVOPDPass : public PassInfoMixin<GCNCreateVOPDPass> {
  MachineFunctionAnalysisManager &AM);
 };
 
+class AMDGPUMarkLastScratchLoadPass
+ : public PassInfoMixin<AMDGPUMarkLastScratchLoadPass> {
+public:
+ PreservedAnalyses run(MachineFunction &MF,
+ MachineFunctionAnalysisManager &AM);
+};
+
 FunctionPass *createAMDGPUAnnotateUniformValuesLegacy();
 
 ModulePass *createAMDGPUPrintfRuntimeBinding();

llvm/lib/Target/AMDGPU/AMDGPUMarkLastScratchLoad.cpp

@@ -25,18 +25,26 @@ using namespace llvm;
 
 namespace {
 
-class AMDGPUMarkLastScratchLoad : public MachineFunctionPass {
+class AMDGPUMarkLastScratchLoad {
 private:
  LiveStacks *LS = nullptr;
  LiveIntervals *LIS = nullptr;
  SlotIndexes *SI = nullptr;
  const SIInstrInfo *SII = nullptr;
 
+public:
+ AMDGPUMarkLastScratchLoad(LiveStacks *LS, LiveIntervals *LIS, SlotIndexes *SI)
+ : LS(LS), LIS(LIS), SI(SI) {}
+ bool run(MachineFunction &MF);
+};
+
+class AMDGPUMarkLastScratchLoadLegacy : public MachineFunctionPass {
 public:
  static char ID;
 
- AMDGPUMarkLastScratchLoad() : MachineFunctionPass(ID) {
- initializeAMDGPUMarkLastScratchLoadPass(*PassRegistry::getPassRegistry());
+ AMDGPUMarkLastScratchLoadLegacy() : MachineFunctionPass(ID) {
+ initializeAMDGPUMarkLastScratchLoadLegacyPass(
+ *PassRegistry::getPassRegistry());
  }
 
  bool runOnMachineFunction(MachineFunction &MF) override;
@@ -56,17 +64,34 @@ class AMDGPUMarkLastScratchLoad : public MachineFunctionPass {
 
 } // end anonymous namespace
 
-bool AMDGPUMarkLastScratchLoad::runOnMachineFunction(MachineFunction &MF) {
+bool AMDGPUMarkLastScratchLoadLegacy::runOnMachineFunction(
+ MachineFunction &MF) {
  if (skipFunction(MF.getFunction()))
  return false;
 
+ auto &LS = getAnalysis<LiveStacksWrapperLegacy>().getLS();
+ auto &LIS = getAnalysis<LiveIntervalsWrapperPass>().getLIS();
+ auto &SI = getAnalysis<SlotIndexesWrapperPass>().getSI();
+
+ return AMDGPUMarkLastScratchLoad(&LS, &LIS, &SI).run(MF);
+}
+
+PreservedAnalyses
+AMDGPUMarkLastScratchLoadPass::run(MachineFunction &MF,
+ MachineFunctionAnalysisManager &MFAM) {
+ auto &LS = MFAM.getResult<LiveStacksAnalysis>(MF);
+ auto &LIS = MFAM.getResult<LiveIntervalsAnalysis>(MF);
+ auto &SI = MFAM.getResult<SlotIndexesAnalysis>(MF);
+
+ AMDGPUMarkLastScratchLoad(&LS, &LIS, &SI).run(MF);
+ return PreservedAnalyses::all();
+}
+
+bool AMDGPUMarkLastScratchLoad::run(MachineFunction &MF) {
  const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
  if (ST.getGeneration() < AMDGPUSubtarget::GFX12)
  return false;
 
- LS = &getAnalysis<LiveStacksWrapperLegacy>().getLS();
- LIS = &getAnalysis<LiveIntervalsWrapperPass>().getLIS();
- SI = &getAnalysis<SlotIndexesWrapperPass>().getSI();
  SII = ST.getInstrInfo();
  SlotIndexes &Slots = *LIS->getSlotIndexes();
 
@@ -130,13 +155,13 @@ bool AMDGPUMarkLastScratchLoad::runOnMachineFunction(MachineFunction &MF) {
  return Changed;
 }
 
-char AMDGPUMarkLastScratchLoad::ID = 0;
+char AMDGPUMarkLastScratchLoadLegacy::ID = 0;
 
-char &llvm::AMDGPUMarkLastScratchLoadID = AMDGPUMarkLastScratchLoad::ID;
+char &llvm::AMDGPUMarkLastScratchLoadID = AMDGPUMarkLastScratchLoadLegacy::ID;
 
-INITIALIZE_PASS_BEGIN(AMDGPUMarkLastScratchLoad, DEBUG_TYPE,
+INITIALIZE_PASS_BEGIN(AMDGPUMarkLastScratchLoadLegacy, DEBUG_TYPE,
  "AMDGPU Mark last scratch load", false, false)
 INITIALIZE_PASS_DEPENDENCY(SlotIndexesWrapperPass)
 INITIALIZE_PASS_DEPENDENCY(LiveStacksWrapperLegacy)
-INITIALIZE_PASS_END(AMDGPUMarkLastScratchLoad, DEBUG_TYPE,
+INITIALIZE_PASS_END(AMDGPUMarkLastScratchLoadLegacy, DEBUG_TYPE,
  "AMDGPU Mark last scratch load", false, false)

llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def

@@ -98,6 +98,7 @@ FUNCTION_PASS_WITH_PARAMS(
 #endif
 MACHINE_FUNCTION_PASS("amdgpu-insert-delay-alu", AMDGPUInsertDelayAluPass())
 MACHINE_FUNCTION_PASS("amdgpu-isel", AMDGPUISelDAGToDAGPass(*this))
+MACHINE_FUNCTION_PASS("amdgpu-mark-last-scratch-load", AMDGPUMarkLastScratchLoadPass())
 MACHINE_FUNCTION_PASS("amdgpu-pre-ra-long-branch-reg", GCNPreRALongBranchRegPass())
 MACHINE_FUNCTION_PASS("amdgpu-reserve-wwm-regs", AMDGPUReserveWWMRegsPass())
 MACHINE_FUNCTION_PASS("amdgpu-rewrite-partial-reg-uses", GCNRewritePartialRegUsesPass())

llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp

@@ -497,7 +497,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUTarget() {
  initializeAMDGPURegBankSelectPass(*PR);
  initializeAMDGPURegBankLegalizePass(*PR);
  initializeSILowerWWMCopiesLegacyPass(*PR);
- initializeAMDGPUMarkLastScratchLoadPass(*PR);
+ initializeAMDGPUMarkLastScratchLoadLegacyPass(*PR);
  initializeSILowerSGPRSpillsLegacyPass(*PR);
  initializeSIFixSGPRCopiesLegacyPass(*PR);
  initializeSIFixVGPRCopiesLegacyPass(*PR);

llvm/test/CodeGen/AMDGPU/vgpr-mark-last-scratch-load.mir

@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3
 # RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -o - %s -run-pass=greedy -run-pass=amdgpu-mark-last-scratch-load -verify-machineinstrs | FileCheck -check-prefix=CHECK %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -o - %s -passes=greedy,amdgpu-mark-last-scratch-load | FileCheck -check-prefix=CHECK %s
 
 --- |
  define amdgpu_cs void @test_spill_12x32() "amdgpu-num-vgpr"="12" {