AArch64: Use Register in FrameLowering (#165188)

Author: arsenm

llvm/lib/Target/AArch64/AArch64FrameLowering.cpp

@@ -1466,7 +1466,7 @@ StackOffset AArch64FrameLowering::resolveFrameOffsetReference(
  return FPOffset;
  }
  FrameReg = RegInfo->hasBasePointer(MF) ? RegInfo->getBaseRegister()
- : (unsigned)AArch64::SP;
+ : MCRegister(AArch64::SP);
 
  return SPOffset;
  }
@@ -1589,30 +1589,30 @@ static bool invalidateRegisterPairing(unsigned Reg1, unsigned Reg2,
 namespace {
 
 struct RegPairInfo {
- unsigned Reg1 = AArch64::NoRegister;
- unsigned Reg2 = AArch64::NoRegister;
+ Register Reg1;
+ Register Reg2;
  int FrameIdx;
  int Offset;
  enum RegType { GPR, FPR64, FPR128, PPR, ZPR, VG } Type;
  const TargetRegisterClass *RC;
 
  RegPairInfo() = default;
 
- bool isPaired() const { return Reg2 != AArch64::NoRegister; }
+ bool isPaired() const { return Reg2.isValid(); }
 
  bool isScalable() const { return Type == PPR || Type == ZPR; }
 };
 
 } // end anonymous namespace
 
-unsigned findFreePredicateReg(BitVector &SavedRegs) {
+MCRegister findFreePredicateReg(BitVector &SavedRegs) {
  for (unsigned PReg = AArch64::P8; PReg <= AArch64::P15; ++PReg) {
  if (SavedRegs.test(PReg)) {
  unsigned PNReg = PReg - AArch64::P0 + AArch64::PN0;
- return PNReg;
+ return MCRegister(PNReg);
  }
  }
- return AArch64::NoRegister;
+ return MCRegister();
 }
 
 // The multivector LD/ST are available only for SME or SVE2p1 targets
@@ -1930,8 +1930,8 @@ bool AArch64FrameLowering::spillCalleeSavedRegisters(
  }
  bool PTrueCreated = false;
  for (const RegPairInfo &RPI : llvm::reverse(RegPairs)) {
- unsigned Reg1 = RPI.Reg1;
- unsigned Reg2 = RPI.Reg2;
+ Register Reg1 = RPI.Reg1;
+ Register Reg2 = RPI.Reg2;
  unsigned StrOpc;
 
  // Issue sequence of spills for cs regs. The first spill may be converted
@@ -1967,7 +1967,7 @@ bool AArch64FrameLowering::spillCalleeSavedRegisters(
  break;
  }
 
- unsigned X0Scratch = AArch64::NoRegister;
+ Register X0Scratch;
  auto RestoreX0 = make_scope_exit([&] {
  if (X0Scratch != AArch64::NoRegister)
  BuildMI(MBB, MI, DL, TII.get(TargetOpcode::COPY), AArch64::X0)
@@ -2147,8 +2147,8 @@ bool AArch64FrameLowering::restoreCalleeSavedRegisters(
 
  bool PTrueCreated = false;
  for (const RegPairInfo &RPI : RegPairs) {
- unsigned Reg1 = RPI.Reg1;
- unsigned Reg2 = RPI.Reg2;
+ Register Reg1 = RPI.Reg1;
+ Register Reg2 = RPI.Reg2;
 
  // Issue sequence of restores for cs regs. The last restore may be converted
  // to a post-increment load later by emitEpilogue if the callee-save stack
@@ -2452,9 +2452,8 @@ void AArch64FrameLowering::determineCalleeSaves(MachineFunction &MF,
  MachineFrameInfo &MFI = MF.getFrameInfo();
  const MCPhysReg *CSRegs = MF.getRegInfo().getCalleeSavedRegs();
 
- unsigned BasePointerReg = RegInfo->hasBasePointer(MF)
- ? RegInfo->getBaseRegister()
- : (unsigned)AArch64::NoRegister;
+ MCRegister BasePointerReg =
+ RegInfo->hasBasePointer(MF) ? RegInfo->getBaseRegister() : MCRegister();
 
  unsigned ExtraCSSpill = 0;
  bool HasUnpairedGPR64 = false;
@@ -2464,7 +2463,7 @@ void AArch64FrameLowering::determineCalleeSaves(MachineFunction &MF,
 
  // Figure out which callee-saved registers to save/restore.
  for (unsigned i = 0; CSRegs[i]; ++i) {
- const unsigned Reg = CSRegs[i];
+ const MCRegister Reg = CSRegs[i];
 
  // Add the base pointer register to SavedRegs if it is callee-save.
  if (Reg == BasePointerReg)
@@ -2478,7 +2477,7 @@ void AArch64FrameLowering::determineCalleeSaves(MachineFunction &MF,
  }
 
  bool RegUsed = SavedRegs.test(Reg);
- unsigned PairedReg = AArch64::NoRegister;
+ MCRegister PairedReg;
  const bool RegIsGPR64 = AArch64::GPR64RegClass.contains(Reg);
  if (RegIsGPR64 || AArch64::FPR64RegClass.contains(Reg) ||
  AArch64::FPR128RegClass.contains(Reg)) {
@@ -2530,8 +2529,8 @@ void AArch64FrameLowering::determineCalleeSaves(MachineFunction &MF,
  AArch64FunctionInfo *AFI = MF.getInfo<AArch64FunctionInfo>();
  // Find a suitable predicate register for the multi-vector spill/fill
  // instructions.
- unsigned PnReg = findFreePredicateReg(SavedRegs);
- if (PnReg != AArch64::NoRegister)
+ MCRegister PnReg = findFreePredicateReg(SavedRegs);
+ if (PnReg.isValid())
  AFI->setPredicateRegForFillSpill(PnReg);
  // If no free callee-save has been found assign one.
  if (!AFI->getPredicateRegForFillSpill() &&
@@ -2566,7 +2565,7 @@ void AArch64FrameLowering::determineCalleeSaves(MachineFunction &MF,
  unsigned PPRCSStackSize = 0;
  const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
  for (unsigned Reg : SavedRegs.set_bits()) {
- auto *RC = TRI->getMinimalPhysRegClass(Reg);
+ auto *RC = TRI->getMinimalPhysRegClass(MCRegister(Reg));
  assert(RC && "expected register class!");
  auto SpillSize = TRI->getSpillSize(*RC);
  bool IsZPR = AArch64::ZPRRegClass.contains(Reg);
@@ -2608,7 +2607,7 @@ void AArch64FrameLowering::determineCalleeSaves(MachineFunction &MF,
  LLVM_DEBUG({
  dbgs() << "*** determineCalleeSaves\nSaved CSRs:";
  for (unsigned Reg : SavedRegs.set_bits())
- dbgs() << ' ' << printReg(Reg, RegInfo);
+ dbgs() << ' ' << printReg(MCRegister(Reg), RegInfo);
  dbgs() << "\n";
  });
 

llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp

@@ -620,7 +620,7 @@ AArch64RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
  return RC;
 }
 
-unsigned AArch64RegisterInfo::getBaseRegister() const { return AArch64::X19; }
+MCRegister AArch64RegisterInfo::getBaseRegister() const { return AArch64::X19; }
 
 bool AArch64RegisterInfo::hasBasePointer(const MachineFunction &MF) const {
  const MachineFrameInfo &MFI = MF.getFrameInfo();

llvm/lib/Target/AArch64/AArch64RegisterInfo.h

@@ -124,7 +124,7 @@ class AArch64RegisterInfo final : public AArch64GenRegisterInfo {
 
  bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override;
  bool hasBasePointer(const MachineFunction &MF) const;
- unsigned getBaseRegister() const;
+ MCRegister getBaseRegister() const;
 
  bool isArgumentRegister(const MachineFunction &MF,
  MCRegister Reg) const override;