[CIR][CIRGen][Builtin][Neon] Lower neon_vrshl_v and neon_vrshlq_v #1151
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bcardosolopes approved these changes Nov 22, 2024
lanza pushed a commit that referenced this pull request Mar 18, 2025
) They are rounding shift of vectors, and shift amount is from the least significant byte of the corresponding element of the second input vector. Thus, it is implemented in [its own ASM ](https://godbolt.org/z/v65sbeKaW). These make them not suitable to be lowered to CIR ShiftOp though it supports vector type now.
terapines-osc-cir pushed a commit to Terapines/clangir that referenced this pull request Sep 2, 2025
…vm#1151) They are rounding shift of vectors, and shift amount is from the least significant byte of the corresponding element of the second input vector. Thus, it is implemented in [its own ASM ](https://godbolt.org/z/v65sbeKaW). These make them not suitable to be lowered to CIR ShiftOp though it supports vector type now.
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They are rounding shift of vectors, and shift amount is from the least significant byte of the corresponding element of the second input vector. Thus, it is implemented in its own ASM . These make them not suitable to be lowered to CIR ShiftOp though it supports vector type now.