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Merged
merged 5 commits into from
Aug 15, 2024
Merged

feat(board): Add Alfredo NoU3 #10134

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77dd6bf
feat(board): Add Alfredo NoU3
SaintSampo Aug 9, 2024
be38aa8
fix(board): added I2C and SS pins to alfredo nou3
SaintSampo Aug 9, 2024
aa9d22d
fix(board): set SPI and I2C pin defs to -1
SaintSampo Aug 14, 2024
a977d07
Merge remote-tracking branch 'upstream/master'
SaintSampo Aug 15, 2024
e03fe45
ci(pre-commit): Apply automatic fixes
pre-commit-ci-lite[bot] Aug 15, 2024
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Merge remote-tracking branch 'upstream/master'
  • Loading branch information
@SaintSampo
SaintSampo committed Aug 15, 2024
commit a977d07031f91b03a3a58dd6bde6410dff5acf6c
161 changes: 161 additions & 0 deletions boards.txt
100755 → 100644
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Expand Up @@ -39242,6 +39242,167 @@ elecrow_crowpanel_7.menu.EraseFlash.all.upload.erase_cmd=-e

##############################################################

circuitart_zero_s3.name=CircuitART Zero S3
circuitart_zero_s3.vid.0=0x303a
circuitart_zero_s3.pid.0=0x80DB

circuitart_zero_s3.bootloader.tool=esptool_py
circuitart_zero_s3.bootloader.tool.default=esptool_py

circuitart_zero_s3.upload.tool=esptool_py
circuitart_zero_s3.upload.tool.default=esptool_py
circuitart_zero_s3.upload.tool.network=esp_ota

circuitart_zero_s3.upload.maximum_size=1310720
circuitart_zero_s3.upload.maximum_data_size=327680
circuitart_zero_s3.upload.flags=
circuitart_zero_s3.upload.extra_flags=
circuitart_zero_s3.upload.use_1200bps_touch=false
circuitart_zero_s3.upload.wait_for_upload_port=false

circuitart_zero_s3.serial.disableDTR=false
circuitart_zero_s3.serial.disableRTS=false

circuitart_zero_s3.build.tarch=xtensa
circuitart_zero_s3.build.bootloader_addr=0x0
circuitart_zero_s3.build.target=esp32s3
circuitart_zero_s3.build.mcu=esp32s3
circuitart_zero_s3.build.core=esp32
circuitart_zero_s3.build.variant=circuitart_zero_s3
circuitart_zero_s3.build.board=CIRCUITART_ZERO_S3

circuitart_zero_s3.build.usb_mode=1
circuitart_zero_s3.build.cdc_on_boot=0
circuitart_zero_s3.build.msc_on_boot=0
circuitart_zero_s3.build.dfu_on_boot=0
circuitart_zero_s3.build.f_cpu=240000000L
circuitart_zero_s3.build.flash_size=16MB
circuitart_zero_s3.build.flash_freq=80m
circuitart_zero_s3.build.flash_mode=dio
circuitart_zero_s3.build.boot=qio
circuitart_zero_s3.build.partitions=default
circuitart_zero_s3.build.defines=
circuitart_zero_s3.build.loop_core=
circuitart_zero_s3.build.event_core=
circuitart_zero_s3.build.flash_type=qio
circuitart_zero_s3.build.psram_type=qspi
circuitart_zero_s3.build.memory_type=qio_qspi

circuitart_zero_s3.menu.LoopCore.1=Core 1
circuitart_zero_s3.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
circuitart_zero_s3.menu.LoopCore.0=Core 0
circuitart_zero_s3.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0

circuitart_zero_s3.menu.EventsCore.1=Core 1
circuitart_zero_s3.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
circuitart_zero_s3.menu.EventsCore.0=Core 0
circuitart_zero_s3.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0

circuitart_zero_s3.menu.USBMode.default=USB-OTG (TinyUSB)
circuitart_zero_s3.menu.USBMode.default.build.usb_mode=0
circuitart_zero_s3.menu.USBMode.hwcdc=Hardware CDC and JTAG
circuitart_zero_s3.menu.USBMode.hwcdc.build.usb_mode=1

circuitart_zero_s3.menu.CDCOnBoot.cdc=Enabled
circuitart_zero_s3.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
circuitart_zero_s3.menu.CDCOnBoot.default=Disabled
circuitart_zero_s3.menu.CDCOnBoot.default.build.cdc_on_boot=0

circuitart_zero_s3.menu.MSCOnBoot.default=Disabled
circuitart_zero_s3.menu.MSCOnBoot.default.build.msc_on_boot=0
circuitart_zero_s3.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode)
circuitart_zero_s3.menu.MSCOnBoot.msc.build.msc_on_boot=1

circuitart_zero_s3.menu.DFUOnBoot.default=Disabled
circuitart_zero_s3.menu.DFUOnBoot.default.build.dfu_on_boot=0
circuitart_zero_s3.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode)
circuitart_zero_s3.menu.DFUOnBoot.dfu.build.dfu_on_boot=1

circuitart_zero_s3.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB)
circuitart_zero_s3.menu.UploadMode.cdc.upload.use_1200bps_touch=true
circuitart_zero_s3.menu.UploadMode.cdc.upload.wait_for_upload_port=true
circuitart_zero_s3.menu.UploadMode.default=UART0 / Hardware CDC
circuitart_zero_s3.menu.UploadMode.default.upload.use_1200bps_touch=false
circuitart_zero_s3.menu.UploadMode.default.upload.wait_for_upload_port=false

circuitart_zero_s3.menu.PSRAM.enabled=Enabled
circuitart_zero_s3.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM
circuitart_zero_s3.menu.PSRAM.disabled=Disabled
circuitart_zero_s3.menu.PSRAM.disabled.build.defines=

circuitart_zero_s3.menu.PartitionScheme.default_16MB=Default (6.25MB APP/3.43MB SPIFFS)
circuitart_zero_s3.menu.PartitionScheme.default_16MB.build.partitions=default_16MB
circuitart_zero_s3.menu.PartitionScheme.default_16MB.upload.maximum_size=6553600
circuitart_zero_s3.menu.PartitionScheme.tinyuf2=TinyUF2 Compatibility (2MB APP/12MB FFAT)
circuitart_zero_s3.menu.PartitionScheme.tinyuf2.build.custom_bootloader=bootloader_tinyuf2
circuitart_zero_s3.menu.PartitionScheme.tinyuf2.build.custom_partitions=partitions_tinyuf2
circuitart_zero_s3.menu.PartitionScheme.tinyuf2.upload.extra_flags=0x410000 "{runtime.platform.path}/variants/{build.variant}/tinyuf2.bin"
circuitart_zero_s3.menu.PartitionScheme.tinyuf2.upload.maximum_size=2097152
circuitart_zero_s3.menu.PartitionScheme.large_spiffs=Large SPIFFS (4.5MB APP/6.93MB SPIFFS)
circuitart_zero_s3.menu.PartitionScheme.large_spiffs.build.partitions=large_spiffs_16MB
circuitart_zero_s3.menu.PartitionScheme.large_spiffs.upload.maximum_size=4718592
circuitart_zero_s3.menu.PartitionScheme.app3M_fat9M_16MB=FFAT (3MB APP/9MB FATFS)
circuitart_zero_s3.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
circuitart_zero_s3.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
circuitart_zero_s3.menu.PartitionScheme.fatflash=Large FFAT (2MB APP/12.5MB FATFS)
circuitart_zero_s3.menu.PartitionScheme.fatflash.build.partitions=ffat
circuitart_zero_s3.menu.PartitionScheme.fatflash.upload.maximum_size=2097152

circuitart_zero_s3.menu.CPUFreq.240=240MHz (WiFi)
circuitart_zero_s3.menu.CPUFreq.240.build.f_cpu=240000000L
circuitart_zero_s3.menu.CPUFreq.160=160MHz (WiFi)
circuitart_zero_s3.menu.CPUFreq.160.build.f_cpu=160000000L
circuitart_zero_s3.menu.CPUFreq.80=80MHz (WiFi)
circuitart_zero_s3.menu.CPUFreq.80.build.f_cpu=80000000L
circuitart_zero_s3.menu.CPUFreq.40=40MHz
circuitart_zero_s3.menu.CPUFreq.40.build.f_cpu=40000000L
circuitart_zero_s3.menu.CPUFreq.20=20MHz
circuitart_zero_s3.menu.CPUFreq.20.build.f_cpu=20000000L
circuitart_zero_s3.menu.CPUFreq.10=10MHz
circuitart_zero_s3.menu.CPUFreq.10.build.f_cpu=10000000L

circuitart_zero_s3.menu.FlashMode.qio=QIO
circuitart_zero_s3.menu.FlashMode.qio.build.flash_mode=dio
circuitart_zero_s3.menu.FlashMode.qio.build.boot=qio
circuitart_zero_s3.menu.FlashMode.dio=DIO
circuitart_zero_s3.menu.FlashMode.dio.build.flash_mode=dio
circuitart_zero_s3.menu.FlashMode.dio.build.boot=dio

circuitart_zero_s3.menu.UploadSpeed.921600=921600
circuitart_zero_s3.menu.UploadSpeed.921600.upload.speed=921600
circuitart_zero_s3.menu.UploadSpeed.115200=115200
circuitart_zero_s3.menu.UploadSpeed.115200.upload.speed=115200
circuitart_zero_s3.menu.UploadSpeed.256000.windows=256000
circuitart_zero_s3.menu.UploadSpeed.256000.upload.speed=256000
circuitart_zero_s3.menu.UploadSpeed.230400.windows.upload.speed=256000
circuitart_zero_s3.menu.UploadSpeed.230400=230400
circuitart_zero_s3.menu.UploadSpeed.230400.upload.speed=230400
circuitart_zero_s3.menu.UploadSpeed.460800.linux=460800
circuitart_zero_s3.menu.UploadSpeed.460800.macosx=460800
circuitart_zero_s3.menu.UploadSpeed.460800.upload.speed=460800
circuitart_zero_s3.menu.UploadSpeed.512000.windows=512000
circuitart_zero_s3.menu.UploadSpeed.512000.upload.speed=512000

circuitart_zero_s3.menu.DebugLevel.none=None
circuitart_zero_s3.menu.DebugLevel.none.build.code_debug=0
circuitart_zero_s3.menu.DebugLevel.error=Error
circuitart_zero_s3.menu.DebugLevel.error.build.code_debug=1
circuitart_zero_s3.menu.DebugLevel.warn=Warn
circuitart_zero_s3.menu.DebugLevel.warn.build.code_debug=2
circuitart_zero_s3.menu.DebugLevel.info=Info
circuitart_zero_s3.menu.DebugLevel.info.build.code_debug=3
circuitart_zero_s3.menu.DebugLevel.debug=Debug
circuitart_zero_s3.menu.DebugLevel.debug.build.code_debug=4
circuitart_zero_s3.menu.DebugLevel.verbose=Verbose
circuitart_zero_s3.menu.DebugLevel.verbose.build.code_debug=5

circuitart_zero_s3.menu.EraseFlash.none=Disabled
circuitart_zero_s3.menu.EraseFlash.none.upload.erase_cmd=
circuitart_zero_s3.menu.EraseFlash.all=Enabled
circuitart_zero_s3.menu.EraseFlash.all.upload.erase_cmd=-e

##############################################################

# Alfredo NoU3

alfredo-nou3.name=Alfredo NoU3
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