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Merged
merged 2 commits into from
Mar 3, 2025
Merged

winch(aarch64): ABI integration #10312

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66d2e5c
winch(aarch64): ABI integration
saulecabrera Feb 28, 2025
84f13c9
Update disas tests
saulecabrera Feb 28, 2025
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78 changes: 76 additions & 2 deletions cranelift/codegen/src/isa/aarch64/abi.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -1123,8 +1123,11 @@ impl ABIMachineSpec for AArch64MachineDeps {
}
}

fn get_regs_clobbered_by_call(_call_conv: isa::CallConv) -> PRegSet {
DEFAULT_AAPCS_CLOBBERS
fn get_regs_clobbered_by_call(call_conv: isa::CallConv) -> PRegSet {
match call_conv {
isa::CallConv::Winch => WINCH_CLOBBERS,
_ => DEFAULT_AAPCS_CLOBBERS,
}
}

fn get_ext_mode(
Expand Down Expand Up @@ -1438,7 +1441,78 @@ const fn default_aapcs_clobbers() -> PRegSet {
.with(vreg_preg(31))
}

const fn winch_clobbers() -> PRegSet {
PRegSet::empty()
.with(xreg_preg(0))
.with(xreg_preg(1))
.with(xreg_preg(2))
.with(xreg_preg(3))
.with(xreg_preg(4))
.with(xreg_preg(5))
.with(xreg_preg(6))
.with(xreg_preg(7))
.with(xreg_preg(8))
.with(xreg_preg(9))
.with(xreg_preg(10))
.with(xreg_preg(11))
.with(xreg_preg(12))
.with(xreg_preg(13))
.with(xreg_preg(14))
.with(xreg_preg(15))
.with(xreg_preg(16))
.with(xreg_preg(17))
// x18 is used to carry platform state and is not allocatable by Winch.
//
// x19 - x27 are considered caller-saved in Winch's calling convention.
.with(xreg_preg(19))
.with(xreg_preg(20))
.with(xreg_preg(21))
.with(xreg_preg(22))
.with(xreg_preg(23))
.with(xreg_preg(24))
.with(xreg_preg(25))
.with(xreg_preg(26))
.with(xreg_preg(27))
// x28 is used as the shadow stack pointer and is considered
// callee-saved.
//
// All vregs are considered caller-saved.
.with(vreg_preg(0))
.with(vreg_preg(1))
.with(vreg_preg(2))
.with(vreg_preg(3))
.with(vreg_preg(4))
.with(vreg_preg(5))
.with(vreg_preg(6))
.with(vreg_preg(7))
.with(vreg_preg(8))
.with(vreg_preg(9))
.with(vreg_preg(10))
.with(vreg_preg(11))
.with(vreg_preg(12))
.with(vreg_preg(13))
.with(vreg_preg(14))
.with(vreg_preg(15))
.with(vreg_preg(16))
.with(vreg_preg(17))
.with(vreg_preg(18))
.with(vreg_preg(19))
.with(vreg_preg(20))
.with(vreg_preg(21))
.with(vreg_preg(22))
.with(vreg_preg(23))
.with(vreg_preg(24))
.with(vreg_preg(25))
.with(vreg_preg(26))
.with(vreg_preg(27))
.with(vreg_preg(28))
.with(vreg_preg(29))
.with(vreg_preg(30))
.with(vreg_preg(31))
}

const DEFAULT_AAPCS_CLOBBERS: PRegSet = default_aapcs_clobbers();
const WINCH_CLOBBERS: PRegSet = winch_clobbers();

fn create_reg_env(enable_pinned_reg: bool) -> MachineEnv {
fn preg(r: Reg) -> PReg {
Expand Down
2 changes: 2 additions & 0 deletions tests/disas/winch/aarch64/br/as_br_if_cond.wat
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Expand Up @@ -8,6 +8,7 @@
;; wasm[0]::function[0]:
;; stp x29, x30, [sp, #-0x10]!
;; mov x29, sp
;; str x28, [sp, #-0x10]!
;; mov x28, sp
;; mov x9, x0
;; sub x28, x28, #0x10
Expand All @@ -17,5 +18,6 @@
;; add x28, x28, #0x10
;; mov sp, x28
;; mov sp, x28
;; ldr x28, [sp], #0x10
;; ldp x29, x30, [sp], #0x10
;; ret
2 changes: 2 additions & 0 deletions tests/disas/winch/aarch64/br/as_br_value.wat
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Expand Up @@ -8,6 +8,7 @@
;; wasm[0]::function[0]:
;; stp x29, x30, [sp, #-0x10]!
;; mov x29, sp
;; str x28, [sp, #-0x10]!
;; mov x28, sp
;; mov x9, x0
;; sub x28, x28, #0x10
Expand All @@ -19,5 +20,6 @@
;; add x28, x28, #0x10
;; mov sp, x28
;; mov sp, x28
;; ldr x28, [sp], #0x10
;; ldp x29, x30, [sp], #0x10
;; ret
2 changes: 2 additions & 0 deletions tests/disas/winch/aarch64/br/as_if_cond.wat
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Expand Up @@ -13,6 +13,7 @@
;; wasm[0]::function[0]:
;; stp x29, x30, [sp, #-0x10]!
;; mov x29, sp
;; str x28, [sp, #-0x10]!
;; mov x28, sp
;; mov x9, x0
;; sub x28, x28, #0x10
Expand All @@ -24,5 +25,6 @@
;; add x28, x28, #0x10
;; mov sp, x28
;; mov sp, x28
;; ldr x28, [sp], #0x10
;; ldp x29, x30, [sp], #0x10
;; ret
12 changes: 7 additions & 5 deletions tests/disas/winch/aarch64/br/as_if_else.wat
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Expand Up @@ -13,6 +13,7 @@
;; wasm[0]::function[0]:
;; stp x29, x30, [sp, #-0x10]!
;; mov x29, sp
;; str x28, [sp, #-0x10]!
;; mov x28, sp
;; mov x9, x0
;; sub x28, x28, #0x18
Expand All @@ -23,14 +24,15 @@
;; stur w3, [x28]
;; ldur w0, [x28, #4]
;; tst w0, w0
;; b.eq #0x40
;; b #0x38
;; 38: ldur w0, [x28]
;; b #0x48
;; 40: mov x16, #4
;; b.eq #0x44
;; b #0x3c
;; 3c: ldur w0, [x28]
;; b #0x4c
;; 44: mov x16, #4
;; mov w0, w16
;; add x28, x28, #0x18
;; mov sp, x28
;; mov sp, x28
;; ldr x28, [sp], #0x10
;; ldp x29, x30, [sp], #0x10
;; ret
12 changes: 7 additions & 5 deletions tests/disas/winch/aarch64/br/as_if_then.wat
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Expand Up @@ -13,6 +13,7 @@
;; wasm[0]::function[0]:
;; stp x29, x30, [sp, #-0x10]!
;; mov x29, sp
;; str x28, [sp, #-0x10]!
;; mov x28, sp
;; mov x9, x0
;; sub x28, x28, #0x18
Expand All @@ -23,14 +24,15 @@
;; stur w3, [x28]
;; ldur w0, [x28, #4]
;; tst w0, w0
;; b.eq #0x44
;; b #0x38
;; 38: mov x16, #3
;; b.eq #0x48
;; b #0x3c
;; 3c: mov x16, #3
;; mov w0, w16
;; b #0x48
;; 44: ldur w0, [x28]
;; b #0x4c
;; 48: ldur w0, [x28]
;; add x28, x28, #0x18
;; mov sp, x28
;; mov sp, x28
;; ldr x28, [sp], #0x10
;; ldp x29, x30, [sp], #0x10
;; ret
2 changes: 2 additions & 0 deletions tests/disas/winch/aarch64/br/as_loop_first.wat
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Expand Up @@ -9,6 +9,7 @@
;; wasm[0]::function[0]:
;; stp x29, x30, [sp, #-0x10]!
;; mov x29, sp
;; str x28, [sp, #-0x10]!
;; mov x28, sp
;; mov x9, x0
;; sub x28, x28, #0x10
Expand All @@ -20,5 +21,6 @@
;; add x28, x28, #0x10
;; mov sp, x28
;; mov sp, x28
;; ldr x28, [sp], #0x10
;; ldp x29, x30, [sp], #0x10
;; ret
6 changes: 4 additions & 2 deletions tests/disas/winch/aarch64/br/br_jump.wat
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Expand Up @@ -16,6 +16,7 @@
;; wasm[0]::function[0]:
;; stp x29, x30, [sp, #-0x10]!
;; mov x29, sp
;; str x28, [sp, #-0x10]!
;; mov x28, sp
;; mov x9, x0
;; sub x28, x28, #0x18
Expand All @@ -34,9 +35,10 @@
;; stur w16, [x28]
;; add x28, x28, #4
;; mov sp, x28
;; b #0x38
;; 54: add x28, x28, #0x18
;; b #0x3c
;; 58: add x28, x28, #0x18
;; mov sp, x28
;; mov sp, x28
;; ldr x28, [sp], #0x10
;; ldp x29, x30, [sp], #0x10
;; ret
14 changes: 8 additions & 6 deletions tests/disas/winch/aarch64/br_if/as_br_if_cond.wat
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Original file line number Diff line number Diff line change
Expand Up @@ -8,6 +8,7 @@
;; wasm[0]::function[0]:
;; stp x29, x30, [sp, #-0x10]!
;; mov x29, sp
;; str x28, [sp, #-0x10]!
;; mov x28, sp
;; mov x9, x0
;; sub x28, x28, #0x10
Expand All @@ -17,15 +18,16 @@
;; mov x16, #1
;; mov w0, w16
;; tst w0, w0
;; b.ne #0x48
;; b #0x34
;; 34: mov x16, #1
;; b.ne #0x4c
;; b #0x38
;; 38: mov x16, #1
;; mov w0, w16
;; tst w0, w0
;; b.ne #0x48
;; b #0x48
;; 48: add x28, x28, #0x10
;; b.ne #0x4c
;; b #0x4c
;; 4c: add x28, x28, #0x10
;; mov sp, x28
;; mov sp, x28
;; ldr x28, [sp], #0x10
;; ldp x29, x30, [sp], #0x10
;; ret
8 changes: 5 additions & 3 deletions tests/disas/winch/aarch64/br_if/as_br_value.wat
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Expand Up @@ -8,6 +8,7 @@
;; wasm[0]::function[0]:
;; stp x29, x30, [sp, #-0x10]!
;; mov x29, sp
;; str x28, [sp, #-0x10]!
;; mov x28, sp
;; mov x9, x0
;; sub x28, x28, #0x10
Expand All @@ -19,10 +20,11 @@
;; mov x16, #1
;; mov w0, w16
;; tst w1, w1
;; b.ne #0x3c
;; b #0x3c
;; 3c: add x28, x28, #0x10
;; b.ne #0x40
;; b #0x40
;; 40: add x28, x28, #0x10
;; mov sp, x28
;; mov sp, x28
;; ldr x28, [sp], #0x10
;; ldp x29, x30, [sp], #0x10
;; ret
18 changes: 10 additions & 8 deletions tests/disas/winch/aarch64/br_if/as_if_cond.wat
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Expand Up @@ -14,6 +14,7 @@
;; wasm[0]::function[0]:
;; stp x29, x30, [sp, #-0x10]!
;; mov x29, sp
;; str x28, [sp, #-0x10]!
;; mov x28, sp
;; mov x9, x0
;; sub x28, x28, #0x18
Expand All @@ -25,18 +26,19 @@
;; mov x16, #1
;; mov w0, w16
;; tst w1, w1
;; b.ne #0x5c
;; b #0x3c
;; 3c: tst w0, w0
;; b.eq #0x54
;; b #0x48
;; 48: mov x16, #2
;; b.ne #0x60
;; b #0x40
;; 40: tst w0, w0
;; b.eq #0x58
;; b #0x4c
;; 4c: mov x16, #2
;; mov w0, w16
;; b #0x5c
;; 54: mov x16, #3
;; b #0x60
;; 58: mov x16, #3
;; mov w0, w16
;; add x28, x28, #0x18
;; mov sp, x28
;; mov sp, x28
;; ldr x28, [sp], #0x10
;; ldp x29, x30, [sp], #0x10
;; ret
8 changes: 5 additions & 3 deletions tests/disas/winch/aarch64/br_if/as_local_set_value.wat
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Expand Up @@ -12,6 +12,7 @@
;; wasm[0]::function[0]:
;; stp x29, x30, [sp, #-0x10]!
;; mov x29, sp
;; str x28, [sp, #-0x10]!
;; mov x28, sp
;; mov x9, x0
;; sub x28, x28, #0x18
Expand All @@ -26,13 +27,14 @@
;; mov x16, #0x11
;; mov w0, w16
;; tst w1, w1
;; b.ne #0x54
;; b #0x48
;; 48: stur w0, [x28, #4]
;; b.ne #0x58
;; b #0x4c
;; 4c: stur w0, [x28, #4]
;; orr x16, xzr, #0xffffffff
;; mov w0, w16
;; add x28, x28, #0x18
;; mov sp, x28
;; mov sp, x28
;; ldr x28, [sp], #0x10
;; ldp x29, x30, [sp], #0x10
;; ret
14 changes: 8 additions & 6 deletions tests/disas/winch/aarch64/br_table/large.wat
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Expand Up @@ -741,6 +741,7 @@
;; wasm[0]::function[0]:
;; stp x29, x30, [sp, #-0x10]!
;; mov x29, sp
;; str x28, [sp, #-0x10]!
;; mov x28, sp
;; mov x9, x0
;; sub x28, x28, #0x18
Expand All @@ -751,14 +752,14 @@
;; ldur w0, [x28, #4]
;; mov x16, #0x6027
;; cmp x0, x16, uxtx
;; b.hs #0x180f4
;; 34: csel x1, xzr, x0, hs
;; b.hs #0x180f8
;; 38: csel x1, xzr, x0, hs
;; csdb
;; adr x16, #0x4c
;; adr x16, #0x50
;; ldrsw x1, [x16, w1, uxtw #2]
;; add x16, x16, x1
;; br x16
;; 4c: .byte 0x9c, 0x80, 0x01, 0x00
;; 50: .byte 0x9c, 0x80, 0x01, 0x00
;; .byte 0xa8, 0x80, 0x01, 0x00
;; .byte 0x9c, 0x80, 0x01, 0x00
;; .byte 0xa8, 0x80, 0x01, 0x00
Expand Down Expand Up @@ -25375,11 +25376,12 @@
;; .byte 0x9c, 0x80, 0x01, 0x00
;; mov x16, #0
;; mov w0, w16
;; b #0x180fc
;; 180f4: mov x16, #1
;; b #0x18100
;; 180f8: mov x16, #1
;; mov w0, w16
;; add x28, x28, #0x18
;; mov sp, x28
;; mov sp, x28
;; ldr x28, [sp], #0x10
;; ldp x29, x30, [sp], #0x10
;; ret
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