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CSR Registers with an integer in their memory map name break CSR Bridge

Status: Open.

#105 In amaranth-lang/amaranth-soc;

· jorolf opened on Sep 8, 2025

AXI Interface Signature

Status: Open.

#103 In amaranth-lang/amaranth-soc;

· jorolf opened on Jun 4, 2025

MemoryMap should allow adding windows with a larger granularity than the parent

improvement

meta:needs-rfc

Status: Open.

#97 In amaranth-lang/amaranth-soc;

· zyp opened on Jul 17, 2024

Monotonic clock

feature

Status: Open.

#90 In amaranth-lang/amaranth-soc;

· whitequark opened on Jun 4, 2024

Tracking issue for RFC 49: GPIO peripheral

Status: Open.

#77 In amaranth-lang/amaranth-soc;

· jfng opened on Mar 8, 2024

The README should be updated

improvement

Status: Open.

#71 In amaranth-lang/amaranth-soc;

· jfng opened on Feb 9, 2024

Tracking issue for RFC 16: CSR register API

Status: Open.

#68 In amaranth-lang/amaranth-soc;

· jfng opened on Feb 6, 2024

Resources on dense memory windows must be sized multiples of "parent" data_width?

Status: Open.

#39 In amaranth-lang/amaranth-soc;

· chenz opened on Mar 30, 2023

Should wishbone.Decoder generate bus errors for unmapped addresses?

improvement

Status: Open.

#38 In amaranth-lang/amaranth-soc;

· chenz opened on Mar 27, 2023

[pre?-RFC] Generic constant-frequency enable generator

design

Status: Open.

#37 In amaranth-lang/amaranth-soc;

· galibert opened on Feb 15, 2023

Constructing Wishbone interface with a single memory window is overly complex / uses redundant parameters

question

Status: Open.

#36 In amaranth-lang/amaranth-soc;

· galibert opened on Feb 14, 2023

[pre-RFC] Ideas for an I2C peripheral interface on Wishbone

design

Status: Open.

#34 In amaranth-lang/amaranth-soc;

· galibert opened on Feb 14, 2023